SACSR: A low power BIST method for sequential circuits / 西安交通大学学报·英文版

ABSTRACT

A novel built-in-self-test,(BIST) method called seeded autonomous cyclic shift register (SACSR) is presented to reduce test power of the sequential circuit. The key idea is to use a pseudorandom pattern generator and several XOR gates to generate seeds that share fewer test vectors. The generated seed is taken XOR operation with a cyclic shift register, and the single input change (SIC) sequence is generated. The proposed scheme is easily implemented and can reduce the switching activities of the circuit under-test. (CUT) greatly. Experimental results on-ISCAS89 benchmarks show that on average more than 63% power reduction can be achieved. It also demonstrates that the generated test vectors attain high fault coverage for stuck-at fault and transition fault coverage with short test length.