A 36-nW Electrocardiogram Anomaly Detector Based on a 1.5-bit Non-Feedback Delta Quantizer for Always-on Cardiac Monitoring.

An always-on electrocardiogram (ECG) anomaly detector (EAD) with ultra-low power (ULP) consumption is proposed for continuous cardiac monitoring applications. The detector is featured with a 1.5-bit non-feedback delta quantizer (DQ) based feature extractor, followed by a multiplier-less convolutional neural network (CNN) engine, which eliminates the traditional high-resolution analog-to-digital converter (ADC) in conventional signal processing systems. The DQ uses a computing-in-capacitor (CIC) subtractor to quantize the sample-to-sample difference of ECG signal into 1.5-bit ternary codes, which is insensitive to low-frequency baseline wandering. The subsequent event-driven classifier is composed of a low-complexity coarse detector and a systolic-array-based CNN engine for ECG anomaly detection. The DQ and the digital CNN are fabricated in 65-nm and 180-nm CMOS technology, respectively, and the two chips are integrated on board through wire bonding. The measured detection accuracy is 90.6% ∼ 91.3% when tested on the MIT-BIH arrhythmia database, identifying three different ECG anomalies. Operating at 1 V and 1.4 V power supplies for the DQ and the digital CNN, respectively, the measured long-term average power consumption of the core circuits is 36 nW, which makes the detector among those state-of-the-art always-on cardiac anomaly detection devices with the lowest power consumption.

A 746 nW ECG Processor ASIC Based on Ternary Neural Network.

This paper presents an ultra-low power electrocardiography (ECG) processor application-specific integrated circuit (ASIC) for the real-time detection of abnormal cardiac rhythms (ACRs). The proposed ECG processor can support wearable or implantable ECG devices for long-term health monitoring. It adopts a derivative-based patient adaptive threshold approach to detect the R peaks in the PQRST complex of ECG signals. Two tiny machine learning classifiers are used for the accurate classification of ACRs. A 3-layer feed-forward ternary neural network (TNN) is designed, which classifies the QRS complex's shape, followed by the adaptive decision logics (DL). The proposed processor requires only 1 KB on-chip memory to store the parameters and ECG data required by the classifiers. The ECG processor has been implemented based on fully-customized near-threshold logic cells using thick-gate transistors in 65-nm CMOS technology. The ASIC core occupies a die area of 1.08 mm2. The measured total power consumption is 746 nW, with 0.8 V power supply at 2.5 kHz real-time operating clock. It can detect 13 abnormal cardiac rhythms with a sensitivity and specificity of 99.10% and 99.5%. The number of detectable ACR types far exceeds the other low power designs in the literature.

A 2.63 µW ECG Processor With Adaptive Arrhythmia Detection and Data Compression for Implantable Cardiac Monitoring Device.

An ultra-low power ECG processor ASIC (application specific integrated circuit) with R-wave detection and data compression is presented, which is designed for the long-term implantable cardiac monitoring (ICM) device for arrhythmia diagnosis. An adaptive derivative-based detection algorithm with low computation overhead for potential arrhythmia recording is proposed to detect arrhythmia with the occasional abnormal heart beats. In order to save as much as possible cardiac information with the limited memory size available in the ICM device, a hierarchical data buffer structure is proposed which saves 3 types of data, including the raw ECG data segments of 2 seconds, compressed ECG data segments of 45 seconds, and R-peak values and interval lengths of >2000 beat cycles. A modified swinging-door-trending (SDT) method is proposed for the ECG data compression. The ASIC has been implemented based on fully-customized near-threshold standard cells using the thick-gate transistors in 65-nm CMOS technology for low dynamic power consumption and leakage. The ASIC core occupies a die area of 1.77 mm2. The measured total power is 2.63 µW, which is among the ECG processors with the lowest core power consumption. It exhibits a relatively high positive precision rate (P+) of 99.3% with a sensitivity of 98.2%, in contrast to the similar designs in literature with the same core power consumption level. Also, an ECG data compression ratio (CR) of up to 17.0 has been achieved, with a good trade-off between the compression efficiency and loss.