Effects of Gluteal Muscle Strengthening Exercise-Based Core Stabilization Training on Pain and Quality of Life in Patients with Chronic Low Back Pain.

Background: The World Health Organization reports that back pain is a major cause of disorder worldwide. It is the most common musculoskeletal disorder with limited pain, muscle tension, and stiffness, and 70-80% of all individuals experience it once in their lifetime, with higher prevalence in women than in men. This study aimed to investigate the effects of gluteal muscle strengthening exercise- based core stabilization training (GSE-based CST) on pain, function, fear-avoidance patterns, and quality of life in patients with chronic back pain. Methods: This study included 34 patients with non-specific chronic low back pain. Seventeen individuals each were included in GSE-based CST and control groups. The GSE-based CST group performed GSE and CST for 15 min, three times a week for four weeks, and the control group performed CST for 30 min a day, three times a week for four weeks. The numeric pain rating scale was used to evaluate pain before and after treatment, Roland-Morris disability questionnaire was used to evaluate function, fear-avoidance beliefs questionnaire was used to evaluate fear-avoidance patterns, and quality of life was measured using the short form-36. Results: In this study, pain, function, and fear-avoidance pattern decreased significantly in both groups (All p < 0.05). During the evaluation of quality of life, both groups showed significant increase in physical and mental factors (p < 0.05). There were significant differences in pain and quality of life (p < 0.05) between the GSE-based CST and control groups. Conclusions: Therefore, GSE-based CST can be used as a basis for effective intervention to enhance pain, function, fear-avoidance patterns, and quality of life, emphasizing the need for gluteal muscle strengthening exercises in patients with non-specific chronic back pain in the future.

Spike Optimization to Improve Properties of Ferroelectric Tunnel Junction Synaptic Devices for Neuromorphic Computing System Applications.

The continuous advancement of Artificial Intelligence (AI) technology depends on the efficient processing of unstructured data, encompassing text, speech, and video. Traditional serial computing systems based on the von Neumann architecture, employed in information and communication technology development for decades, are not suitable for the concurrent processing of massive unstructured data tasks with relatively low-level operations. As a result, there arises a pressing need to develop novel parallel computing systems. Recently, there has been a burgeoning interest among developers in emulating the intricate operations of the human brain, which efficiently processes vast datasets with remarkable energy efficiency. This has led to the proposal of neuromorphic computing systems. Of these, Spiking Neural Networks (SNNs), designed to closely resemble the information processing mechanisms of biological neural networks, are subjects of intense research activity. Nevertheless, a comprehensive investigation into the relationship between spike shapes and Spike-Timing-Dependent Plasticity (STDP) to ensure efficient synaptic behavior remains insufficiently explored. In this study, we systematically explore various input spike types to optimize the resistive memory characteristics of Hafnium-based Ferroelectric Tunnel Junction (FTJ) devices. Among the various spike shapes investigated, the square-triangle (RT) spike exhibited good linearity and symmetry, and a wide range of weight values could be realized depending on the offset of the RT spike. These results indicate that the spike shape serves as a crucial indicator in the alteration of synaptic connections, representing the strength of the signals.

Yttrium Doping Effects on Ferroelectricity and Electric Properties of As-Deposited Hf1-xZrxO2 Thin Films via Atomic Layer Deposition.

Hf1-xZrxO2 (HZO) thin films are versatile materials suitable for advanced ferroelectric semiconductor devices. Previous studies have shown that the ferroelectricity of HZO thin films can be stabilized by doping them with group III elements at low concentrations. While doping with Y improves the ferroelectric properties, there has been limited research on Y-HZO thin films fabricated using atomic layer deposition (ALD). In this study, we investigated the effects of Y-doping cycles on the ferroelectric and electrical properties of as-deposited Y-HZO thin films with varying compositions fabricated through ALD. The Y-HZO thin films were stably crystallized without the need for post-thermal treatment and exhibited transition behavior depending on the Y-doping cycle and initial composition ratio of the HZO thin films. These Y-HZO thin films offer several advantages, including enhanced dielectric constant, leakage current density, and improved endurance. Moreover, the optimized Y-doping cycle induced a phase transformation that resulted in Y-HZO thin films with improved ferroelectric properties, exhibiting stable behavior without fatigue for up to 1010 cycles. These as-deposited Y-HZO thin films show promise for applications in semiconductor devices that require high ferroelectric properties, excellent electrical properties, and reliable performance with a low thermal budget.

Improvement of Resistance Change Memory Characteristics in Ferroelectric and Antiferroelectric (like) Parallel Structures.

Recently, considerable attention has been paid to the development of advanced technologies such as artificial intelligence (AI) and big data, and high-density, high-speed storage devices are being extensively studied to realize the technology. Ferroelectrics are promising non-volatile memory materials because of their ability to maintain polarization, even when an external electric field is removed. Recently, it has been reported that HfO2 thin films compatible with complementary metal-oxide-semiconductor (CMOS) processes exhibit ferroelectricity even at a thickness of less than 10 nm. Among the ferroelectric-based memories, ferroelectric tunnel junctions are attracting attention as ideal devices for improving integration and miniaturization due to the advantages of a simple metal-ferroelectric-metal two-terminal structure and low ultra-low power driving through tunneling. The FTJs are driven by adjusting the tunneling electrical resistance through partial polarization switching. Theoretically and experimentally, a large memory window in a broad coercive field and/or read voltage is required to induce sophisticated partial-polarization switching. Notably, antiferroelectrics (like) have different switching properties than ferroelectrics, which are generally applied to ferroelectric tunnel junctions. The memory features of ferroelectric tunnel junctions are expected to be improved through a broad coercive field when the switching characteristics of the ferroelectric and antiferroelectric (like) are utilized concurrently. In this study, the implementation of multiresistance states was improved by driving the ferroelectric and antiferroelectric (like) devices in parallel. Additionally, by modulating the area ratio of ferroelectric and antiferroelectric (like), the memory window size was increased, and controllability was enhanced by increasing the switchable voltage region. In conclusion, we suggest that ferroelectric and antiferroelectric (like) parallel structures may overcome the limitations of the multiresistance state implementation of existing ferroelectrics.

Si-Doped HfO2-Based Ferroelectric Tunnel Junctions with a Composite Energy Barrier for Non-Volatile Memory Applications.

Ferroelectric tunnel junctions (FTJs) have attracted attention as devices for advanced memory applications owing to their high operating speed, low operating energy, and excellent scalability. In particular, hafnia ferroelectric materials are very promising because of their high remanent polarization (below 10 nm) and high compatibility with complementary metal-oxide-semiconductor (CMOS) processes. In this study, a Si-doped HfO2-based FTJ device with a metal-ferroelectric-insulator-semiconductor (MFIS) structure was proposed to maximize the tunneling electro-resistance (TER) effect. The potential barrier modulation effect under applied varying voltage was analyzed, and the possibility of its application as a non-volatile memory device was presented through stability assessments such as endurance and retention tests.

Synaptic Characteristic of Hafnia-Based Ferroelectric Tunnel Junction Device for Neuromorphic Computing Application.

Owing to the 4th Industrial Revolution, the amount of unstructured data, such as voice and video data, is rapidly increasing. Brain-inspired neuromorphic computing is a new computing method that can efficiently and parallelly process rapidly increasing data. Among artificial neural networks that mimic the structure of the brain, the spiking neural network (SNN) is a network that imitates the information-processing method of biological neural networks. Recently, memristors have attracted attention as synaptic devices for neuromorphic computing systems. Among them, the ferroelectric doped-HfO2-based ferroelectric tunnel junction (FTJ) is considered as a strong candidate for synaptic devices due to its advantages, such as complementary metal-oxide-semiconductor device/process compatibility, a simple two-terminal structure, and low power consumption. However, research on the spiking operations of FTJ devices for SNN applications is lacking. In this study, the implementation of long-term depression and potentiation as the spike timing-dependent plasticity (STDP) rule in the FTJ device was successful. Based on the measured data, a CrossSim simulator was used to simulate the classification of handwriting images. With a high accuracy of 95.79% for the Mixed National Institute of Standards and Technology (MNIST) dataset, the simulation results demonstrate that our device is capable of differentiating between handwritten images. This suggests that our FTJ device can be used as a synaptic device for implementing an SNN.

Origin of high photoconductive gain in fully transparent heterojunction nanocrystalline oxide image sensors and interconnects.

A technique for invisible image capture using a photosensor array based on transparent conducting oxide semiconductor thin-film transistors and transparent interconnection technologies is presented. A transparent conducting layer is employed for the sensor electrodes as well as interconnection in the array, providing about 80% transmittance at visible-light wavelengths. The phototransistor is a Hf-In-Zn-O/In-Zn-O heterostructure yielding a high quantum-efficiency in the visible range.

High-performance low-cost back-channel-etch amorphous gallium-indium-zinc oxide thin-film transistors by curing and passivation of the damaged back channel.

High-performance, low-cost amorphous gallium-indium-zinc oxide (a-GIZO) thin-film-transistor (TFT) technology is required for the next generation of active-matrix organic light-emitting diodes. A back-channel-etch structure is the most appropriate device structure for high-performance, low-cost a-GIZO TFT technology. However, channel damage due to source/drain etching and passivation-layer deposition has been a critical issue. To solve this problem, the present work focuses on overall back-channel processes, such as back-channel N2O plasma treatment, SiOx passivation deposition, and final thermal annealing. This work has revealed the dependence of a-GIZO TFT characteristics on the N2O plasma radio-frequency (RF) power and frequency, the SiH4 flow rate in the SiOx deposition process, and the final annealing temperature. On the basis of these results, a high-performance a-GIZO TFT with a field-effect mobility of 35.7 cm(2) V(-1) s(-1), a subthreshold swing of 185 mV dec(-1), a switching ratio exceeding 10(7), and a satisfactory reliability was successfully fabricated. The technology developed in this work can be realized using the existing facilities of active-matrix liquid-crystal display industries.

High-performance nanowire oxide photo-thin film transistor.

A gate-modulated nanowire oxide photosensor is fabricated by electron-beam lithography and conventional dry etch processing.. The device characteristics are good, including endurance of up to 10(6) test cycles, and gate-pulse excitation is used to remove persistent photoconductivity. The viability of nanowire oxide phototransistors for high speed and high resolution applications is demonstrated, thus potentially expanding the scope of exploitation of touch-free interactive displays.

Gated three-terminal device architecture to eliminate persistent photoconductivity in oxide semiconductor photosensor arrays.

The composition of amorphous oxide semiconductors, which are well known for their optical transparency, can be tailored to enhance their absorption and induce photoconductivity for irradiation with green, and shorter wavelength light. In principle, amorphous oxide semiconductor-based thin-film photoconductors could hence be applied as photosensors. However, their photoconductivity persists for hours after illumination has been removed, which severely degrades the response time and the frame rate of oxide-based sensor arrays. We have solved the problem of persistent photoconductivity (PPC) by developing a gated amorphous oxide semiconductor photo thin-film transistor (photo-TFT) that can provide direct control over the position of the Fermi level in the active layer. Applying a short-duration (10 ns) voltage pulse to these devices induces electron accumulation and accelerates their recombination with ionized oxygen vacancy sites, which are thought to cause PPC. We have integrated these photo-TFTs in a transparent active-matrix photosensor array that can be operated at high frame rates and that has potential applications in contact-free interactive displays.

A simple device unit consisting of all NiO storage and switch elements for multilevel terabit nonvolatile random access memory.

Present charge-based silicon memories are unlikely to reach terabit densities because of scaling limits. As the feature size of memory shrinks to just tens of nanometers, there is insufficient volume available to store charge. Also, process temperatures higher than 800 °C make silicon incompatible with three-dimensional (3D) stacking structures. Here we present a device unit consisting of all NiO storage and switch elements for multilevel terabit nonvolatile random access memory using resistance switching. It is demonstrated that NiO films are scalable to around 30 nm and compatible with multilevel cell technology. The device unit can be a building block for 3D stacking structure because of its simple structure and constituent, high performance, and process temperature lower than 300 °C. Memory resistance switching of NiO storage element is accompanied by an increase in density of grain boundary while threshold resistance switching of NiO switch element is controlled by current flowing through NiO film.

Electrical manipulation of nanofilaments in transition-metal oxides for resistance-based memory.

The fabrication of controlled nanostructures such as quantum dots, nanotubes, nanowires, and nanopillars has progressed rapidly over the past 10 years. However, both bottom-up and top-down methods to integrate the nanostructures are met with several challenges. For practical applications with the high level of the integration, an approach that can fabricate the required structures locally is desirable. In addition, the electrical signal to construct and control the nanostructures can provide significant advantages toward the stability and ordering. Through experiments on the negative resistance switching phenomenon in Pt-NiO-Pt structures, we have fabricated nanofilament channels that can be electrically connected or disconnected. Various analyses indicate that the nanofilaments are made of nickel and are formed at the grain boundaries. The scaling behaviors of the nickel nanofilaments were closely examined, with respect to the switching time, power, and resistance. In particular, the 100 nm x 100 nm cell was switchable on the nanosecond scale, making them ideal for the basis for high-speed, high-density, nonvolatile memory applications.