Diagnosis of heart diseases: A fuzzy-logic-based approach.

Cardiovascular diseases (CVD) also known as heart disease are now the leading cause of death in the world. This paper presents research for the design and creation of a fuzzy logic-based expert system for the prognosis and diagnosis of heart disease that is precise, economical, and effective. This system entails a fuzzification module, knowledge base, inference engine, and defuzzification module where seven attributes such as chest pain type, HbA1c (Haemoglobin A1c), HDL (high-density lipoprotein), LDL (low-density lipoprotein), heart rate, age, and blood pressure are considered as input to the system. With the aid of the available literature and extensive consultation with medical experts in this field, an enriched knowledge database has been created with a sufficient number of IF-THEN rules for the diagnosis of heart disease. The inference engine then activates the appropriate IF-THEN rule from the knowledge base and determines the output value using the appropriate defuzzification technique after the fuzzification module fuzzifies each input depending on the appropriate membership function. Moreover, the fusion of web-based technology makes it suitable and cost-effective for the prognosis of heart disease for a patient and then he can take his decision for addressing the problem based on the status of his heart. On the other hand, it can also assist a medical practitioner to reach a more accurate conclusion regarding the treatment of heart disease for a patient. The Mamdani inference method has been used to evaluate the results. The system is tested with the Cleveland dataset and cross-checked with the in-field dataset. Compared with the other existing expert systems, the proposed method performs 98.08% accurately and can make accurate decisions for diagnosing heart diseases.

Area efficient camouflaging technique for securing IC reverse engineering.

Reverse engineering is a burning issue in Integrated Circuit (IC) design and manufacturing. In the semiconductor industry, it results in a revenue loss of billions of dollars every year. In this work, an area efficient, high-performance IC camouflaging technique is proposed at the physical design level to combat the integrated circuit's reverse engineering. An attacker may not identify various logic gates in the layout due to similar image output. In addition, a dummy or true contact-based technique is implemented for optimum outcomes. A library of gates is proposed that contains the various camouflaged primitive gates developed by a combination of using the metal routing technique along with the dummy contact technique. This work shows the superiority of the proposed technique's performance matrix with those of existing works regarding resource burden, area, and delay. The proposed library is expected to make open source to help ASIC designers secure IC design and save colossal revenue loss.

Design of a BIST implemented AES crypto-processor ASIC.

This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.

A Novel Byte-Substitution Architecture for the AES Cryptosystem.

The performance of Advanced Encryption Standard (AES) mainly depends on speed, area and power. The S-box represents an important factor that affects the performance of AES on each of these factors. A number of techniques have been presented in the literature, which have attempted to improve the performance of the S-box byte-substitution. This paper proposes a new S-box architecture, defining it as ultra low power, robustly parallel and highly efficient in terms of area. The architecture is discussed for both CMOS and FPGA platforms, and the pipelined architecture of the proposed S-box is presented for further time savings and higher throughput along with higher hardware resources utilization. A performance analysis and comparison of the proposed architecture is also conducted with those achieved by the existing techniques. The results of the comparison verify the outperformance of the proposed architecture in terms of power, delay and size.