Low-Power MEMS-Based Pierce Oscillator Using a 61-MHz Capacitive-Gap Disk Resonator.

A 61-MHz Pierce oscillator constructed in 0.35- [Formula: see text] CMOS technology and referenced to a polysilicon surface-micromachined capacitive-gap-transduced wine-glass disk resonator has achieved phase noise marks of -119 dBc/Hz at 1-kHz offset and -139 dBc/Hz at far-from-carrier offsets. When divided down to 13 MHz, this corresponds to -132 dBc/Hz at 1-kHz offset from the carrier and -152 dBc/Hz far-from-carrier, sufficient for mobile phone reference oscillator applications, using a single MEMS resonator, i.e., without the need to array multiple resonators. Key to achieving these marks is a Pierce-based circuit design that harnesses a MEMS-enabled input-to-output shunt capacitance more than 100× smaller than exhibited by macroscopic quartz crystals to enable enough negative resistance to instigate and sustain oscillation while consuming only [Formula: see text] of power-a reduction of  âˆ¼ 4.5× over previous work. Increasing the bias voltage of the resonator by 1.25 V further reduces power consumption to [Formula: see text] at the cost of only a few decibels in far-from-carrier phase noise. This oscillator achieves a 1-kHz-offset figure of merit (FOM) of -231 dB, which is now the best among published chip-scale oscillators to date. A complete linear circuit analysis quantifies the influence of resonator input-to-output shunt capacitance on power consumption and predicts further reductions in power consumption via reduction of electrode-to-resonator transducer gaps and bond pad sizes. The demonstrated phase noise and power consumption posted by this tiny MEMS-based oscillator are attractive as potential enablers for low-power "set-and-forget" autonomous sensor networks and embedded radios.

Wireless Recording in the Peripheral Nervous System with Ultrasonic Neural Dust.

The emerging field of bioelectronic medicine seeks methods for deciphering and modulating electrophysiological activity in the body to attain therapeutic effects at target organs. Current approaches to interfacing with peripheral nerves and muscles rely heavily on wires, creating problems for chronic use, while emerging wireless approaches lack the size scalability necessary to interrogate small-diameter nerves. Furthermore, conventional electrode-based technologies lack the capability to record from nerves with high spatial resolution or to record independently from many discrete sites within a nerve bundle. Here, we demonstrate neural dust, a wireless and scalable ultrasonic backscatter system for powering and communicating with implanted bioelectronics. We show that ultrasound is effective at delivering power to mm-scale devices in tissue; likewise, passive, battery-less communication using backscatter enables high-fidelity transmission of electromyogram (EMG) and electroneurogram (ENG) signals from anesthetized rats. These results highlight the potential for an ultrasound-based neural interface system for advancing future bioelectronics-based therapies.

Powering and communication for OMNI: A distributed and modular closed-loop neuromodulation device.

A distributed, modular, intelligent, and efficient neuromodulation device, called OMNI, is presented. It supports closed-loop recording and stimulation on 256 channels from up to 4 physically distinct neuromodulation modules placed in any configuration around the brain, hence offering the capability of addressing neural disorders that are presented at the network level. The specific focus of this paper is the communication and power distribution network that enables the modular and distributed nature of the device.

Ultrasonic beamforming system for interrogating multiple implantable sensors.

In this paper, we present an ultrasonic beamforming system capable of interrogating individual implantable sensors via backscatter in a distributed, ultrasound-based recording platform known as Neural Dust [1]. A custom ASIC drives a 7 × 2 PZT transducer array with 3 cycles of 32V square wave with a specific programmable time delay to focus the beam at the 800mm neural dust mote placed 50mm away. The measured acoustic-to-electrical conversion efficiency of the receive mote in water is 0.12% and the overall system delivers 26.3% of the power from the 1.8V power supply to the transducer drive output, consumes 0.75µJ in each transmit phase, and has a 0.5% change in the backscatter per volt applied to the input of the backscatter circuit. Further miniaturization of both the transmit array and the receive mote can pave the way for a wearable, chronic sensing and neuromodulation system.

Model validation of untethered, ultrasonic neural dust motes for cortical recording.

A major hurdle in brain-machine interfaces (BMI) is the lack of an implantable neural interface system that remains viable for a substantial fraction of the user's lifetime. Recently, sub-mm implantable, wireless electromagnetic (EM) neural interfaces have been demonstrated in an effort to extend system longevity. However, EM systems do not scale down in size well due to the severe inefficiency of coupling radio-waves at those scales within tissue. This paper explores fundamental system design trade-offs as well as size, power, and bandwidth scaling limits of neural recording systems built from low-power electronics coupled with ultrasonic power delivery and backscatter communication. Such systems will require two fundamental technology innovations: (1) 10-100 µm scale, free-floating, independent sensor nodes, or neural dust, that detect and report local extracellular electrophysiological data via ultrasonic backscattering and (2) a sub-cranial ultrasonic interrogator that establishes power and communication links with the neural dust. We provide experimental verification that the predicted scaling effects follow theory; (127 µm)(3) neural dust motes immersed in water 3 cm from the interrogator couple with 0.002064% power transfer efficiency and 0.04246 ppm backscatter, resulting in a maximum received power of ∼0.5 µW with ∼1 nW of change in backscatter power with neural activity. The high efficiency of ultrasonic transmission can enable the scaling of the sensing nodes down to 10s of micrometer. We conclude with a brief discussion of the application of neural dust for both central and peripheral nervous system recordings, and perspectives on future research directions.

Miniaturizing Ultrasonic System for Portable Health Care and Fitness.

We present a miniaturized portable ultrasonic imager that uses a custom ASIC and a piezoelectric transducer array to transmit and capture 2-D sonographs. The ASIC, fabricated in 0.18 µm 32 V CMOS process, contains 7 identical channels, each with high-voltage level-shifters, high-voltage DC-DC converters, digital TX beamformer, and RX front-end. The chip is powered by a single 1.8 V supply and generates 5 V and 32 V internally using on-chip charge pumps with an efficiency of 33% to provide 32 V pulses for driving a bulk piezoelectric transducer array. The assembled prototype can operate up to 40 MHz, with beamformer delay resolution of 5 ns, and has a measured sensitivity of 225 nV/Pa , minimum detectable signal of 622 Pa assuming 12 dB SNR ( 4σ larger than the noise level), and data acquisition time of 21.3 ms. The system can image human tissue as deep as 5 cm while consuming less than 16.5 µJ per pulse-echo measurement. The high energy efficiency of the imager can enable a number of consumer applications.

Beamforming approaches for untethered, ultrasonic neural dust motes for cortical recording: a simulation study.

In this paper, we examine the use of beamforming techniques to interrogate a multitude of neural implants in a distributed, ultrasound-based intra-cortical recording platform known as Neural Dust. We propose a general framework to analyze system design tradeoffs in the ultrasonic beamformer that extracts neural signals from modulated ultrasound waves that are backscattered by free-floating neural dust (ND) motes. Simulations indicate that high-resolution linearly-constrained minimum variance beamforming sufficiently suppresses interference from unselected ND motes and can be incorporated into the ND-based cortical recording system.

Physical principles for scalable neural recording.

Simultaneously measuring the activities of all neurons in a mammalian brain at millisecond resolution is a challenge beyond the limits of existing techniques in neuroscience. Entirely new approaches may be required, motivating an analysis of the fundamental physical constraints on the problem. We outline the physical principles governing brain activity mapping using optical, electrical, magnetic resonance, and molecular modalities of neural recording. Focusing on the mouse brain, we analyze the scalability of each method, concentrating on the limitations imposed by spatiotemporal resolution, energy dissipation, and volume displacement. Based on this analysis, all existing approaches require orders of magnitude improvement in key parameters. Electrical recording is limited by the low multiplexing capacity of electrodes and their lack of intrinsic spatial resolution, optical methods are constrained by the scattering of visible light in brain tissue, magnetic resonance is hindered by the diffusion and relaxation timescales of water protons, and the implementation of molecular recording is complicated by the stochastic kinetics of enzymes. Understanding the physical limits of brain activity mapping may provide insight into opportunities for novel solutions. For example, unconventional methods for delivering electrodes may enable unprecedented numbers of recording sites, embedded optical devices could allow optical detectors to be placed within a few scattering lengths of the measured neurons, and new classes of molecularly engineered sensors might obviate cumbersome hardware architectures. We also study the physics of powering and communicating with microscale devices embedded in brain tissue and find that, while radio-frequency electromagnetic data transmission suffers from a severe power-bandwidth tradeoff, communication via infrared light or ultrasound may allow high data rates due to the possibility of spatial multiplexing. The use of embedded local recording and wireless data transmission would only be viable, however, given major improvements to the power efficiency of microelectronic devices.

Ultra-efficient 10 Gb/s hybrid integrated silicon photonic transmitter and receiver.

Using low parasitic microsolder bumping, we hybrid integrated efficient photonic devices from different platforms with advanced 40 nm CMOS VLSI circuits to build ultra-low power silicon photonic transmitters and receivers for potential applications in high performance inter/intra-chip interconnects. We used a depletion racetrack ring modulator with improved electro-optic efficiency to allow stepper optical photo lithography for reduced fabrication complexity. Integrated with a low power cascode 2 V CMOS driver, the hybrid silicon photonic transmitter achieved better than 7 dB extinction ratio for 10 Gbps operation with a record low power consumption of 1.35 mW. A received power penalty of about 1 dB was measured for a BER of 10(-12) compared to an off-the-shelf lightwave LiNOb3 transmitter, which comes mostly from the non-perfect extinction ratio. Similarly, a Ge waveguide detector fabricated using 130 nm SOI CMOS process was integrated with low power VLSI circuits using hybrid bonding. The all CMOS hybrid silicon photonic receiver achieved sensitivity of -17 dBm for a BER of 10(-12) at 10 Gbps, consuming an ultra-low power of 3.95 mW (or 395 fJ/bit in energy efficiency). The scalable hybrid integration enables continued photonic device improvements by leveraging advanced CMOS technologies with maximum flexibility, which is critical for developing ultra-low power high performance photonic interconnects for future computing systems.

A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems.

We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible.