Reducing charge noise in quantum dots by using thin silicon quantum wells.

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a 28Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick 28Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 µeV/Hz½ at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to CZ-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system.

Atomic fluctuations lifting the energy degeneracy in Si/SiGe quantum dots.

Electron spins in Si/SiGe quantum wells suffer from nearly degenerate conduction band valleys, which compete with the spin degree of freedom in the formation of qubits. Despite attempts to enhance the valley energy splitting deterministically, by engineering a sharp interface, valley splitting fluctuations remain a serious problem for qubit uniformity, needed to scale up to large quantum processors. Here, we elucidate and statistically predict the valley splitting by the holistic integration of 3D atomic-level properties, theory and transport. We find that the concentration fluctuations of Si and Ge atoms within the 3D landscape of Si/SiGe interfaces can explain the observed large spread of valley splitting from measurements on many quantum dot devices. Against the prevailing belief, we propose to boost these random alloy composition fluctuations by incorporating Ge atoms in the Si quantum well to statistically enhance valley splitting.

Universal control of a six-qubit quantum processor in silicon.

Future quantum computers capable of solving relevant problems will require a large number of qubits that can be operated reliably1. However, the requirements of having a large qubit count and operating with high fidelity are typically conflicting. Spins in semiconductor quantum dots show long-term promise2,3 but demonstrations so far use between one and four qubits and typically optimize the fidelity of either single- or two-qubit operations, or initialization and readout4-11. Here, we increase the number of qubits and simultaneously achieve respectable fidelities for universal operation, state preparation and measurement. We design, fabricate and operate a six-qubit processor with a focus on careful Hamiltonian engineering, on a high level of abstraction to program the quantum circuits, and on efficient background calibration, all of which are essential to achieve high fidelities on this extended system. State preparation combines initialization by measurement and real-time feedback with quantum-non-demolition measurements. These advances will enable testing of increasingly meaningful quantum protocols and constitute a major stepping stone towards large-scale quantum computers.

Classification with a disordered dopant-atom network in silicon.

Classification is an important task at which both biological and artificial neural networks excel1,2. In machine learning, nonlinear projection into a high-dimensional feature space can make data linearly separable3,4, simplifying the classification of complex features. Such nonlinear projections are computationally expensive in conventional computers. A promising approach is to exploit physical materials systems that perform this nonlinear projection intrinsically, because of their high computational density5, inherent parallelism and energy efficiency6,7. However, existing approaches either rely on the systems' time dynamics, which requires sequential data processing and therefore hinders parallel computation5,6,8, or employ large materials systems that are difficult to scale up7. Here we use a parallel, nanoscale approach inspired by filters in the brain1 and artificial neural networks2 to perform nonlinear classification and feature extraction. We exploit the nonlinearity of hopping conduction9-11 through an electrically tunable network of boron dopant atoms in silicon, reconfiguring the network through artificial evolution to realize different computational functions. We first solve the canonical two-input binary classification problem, realizing all Boolean logic gates12 up to room temperature, demonstrating nonlinear classification with the nanomaterial system. We then evolve our dopant network to realize feature filters2 that can perform four-input binary classification on the Modified National Institute of Standards and Technology handwritten digit database. Implementation of our material-based filters substantially improves the classification accuracy over that of a linear classifier directly applied to the original data13. Our results establish a paradigm of silicon-based electronics for small-footprint and energy-efficient computation14.

Palladium gates for reproducible quantum dots in silicon.

We replace the established aluminium gates for the formation of quantum dots in silicon with gates made from palladium. We study the morphology of both aluminium and palladium gates with transmission electron microscopy. The native aluminium oxide is found to be formed all around the aluminium gates, which could lead to the formation of unintentional dots. Therefore, we report on a novel fabrication route that replaces aluminium and its native oxide by palladium with atomic-layer-deposition-grown aluminium oxide. Using this approach, we show the formation of low-disorder gate-defined quantum dots, which are reproducibly fabricated. Furthermore, palladium enables us to further shrink the gate design, allowing us to perform electron transport measurements in the few-electron regime in devices comprising only two gate layers, a major technological advancement. It remains to be seen, whether the introduction of palladium gates can improve the excellent results on electron and nuclear spin qubits defined with an aluminium gate stack.

A fabrication guide for planar silicon quantum dot heterostructures.

We describe important considerations to create top-down fabricated planar quantum dots in silicon, often not discussed in detail in literature. The subtle interplay between intrinsic material properties, interfaces and fabrication processes plays a crucial role in the formation of electrostatically defined quantum dots. Processes such as oxidation, physical vapor deposition and atomic-layer deposition must be tailored in order to prevent unwanted side effects such as defects, disorder and dewetting. In two directly related manuscripts written in parallel we use techniques described in this work to create depletion-mode quantum dots in intrinsic silicon, and low-disorder silicon quantum dots defined with palladium gates. While we discuss three different planar gate structures, the general principles also apply to 0D and 1D systems, such as self-assembled islands and nanowires.

Passivation and characterization of charge defects in ambipolar silicon quantum dots.

In this Report we show the role of charge defects in the context of the formation of electrostatically defined quantum dots. We introduce a barrier array structure to probe defects at multiple locations in a single device. We measure samples both before and after an annealing process which uses an Al2O3 overlayer, grown by atomic layer deposition. After passivation of the majority of charge defects with annealing we can electrostatically define hole quantum dots up to 180 nm in length. Our ambipolar structures reveal amphoteric charge defects that remain after annealing with charging energies of 10 meV in both the positive and negative charge state.

A highly pH-sensitive nanowire field-effect transistor based on silicon on insulator.

BACKGROUND: An experimental and theoretical study of a silicon-nanowire field-effect transistor made of silicon on insulator by CMOS-compatible methods is presented. RESULTS: A maximum Nernstian sensitivity to pH change of 59 mV/pH was obtained experimentally. The maximum charge sensitivity of the sensor was estimated to be on the order of a thousandth of the electron charge in subthreshold mode. CONCLUSION: The sensitivity obtained for our sensor built in the CMOS-compatible top-down approach does not yield to the one of sensors built in bottom-up approaches. This provides a good background for the development of CMOS-compatible probes with primary signal processing on-chip.