Abnormal Threshold Voltage Shifts in P-Channel Low-Temperature Polycrystalline Silicon Thin Film Transistors Under Negative Bias Temperature Stress.

In this research, we have investigated the instability of P-channel low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS TFTs) with double-layer SiO2/SiNx dielectrics. A negative gate bias temperature instability (NBTI) stress was applied and a turn-around behavior phenomenon was observed in the Threshold Voltage Shift (Vth). A positive threshold voltage shift occurs in the first stage, resulting from the negative charge trapping at the SiNx/SiO2 dielectric interface being dominant over the positive charge trapping at dielectric/Poly-Si interface. Following a stress time of 7000 s, the Vth switches to the negative voltage direction, which is "turn-around" behavior. In the second stage, the Vth moves from -1.63 V to -2 V, overwhelming the NBTI effect that results in the trapping of positive charges at the dielectric/Poly-Si interface states and generating grain-boundary trap states and oxide traps.

Temperature-dependent electrical characteristics of c-Si and CIGS solar cells.

We characterized the electrical behavior of crystalline silicon (c-Si) and Cu(In(1-x)Ga(x))Se2 (CIGS) solar cells by current-voltage (I-V) and capacitance-voltage (C-V) methods. We investigated the temperature-dependent carrier transport mechanism by determining the parameters of ideality factor (n) and activation energy (E(a)) deduced from I-V measurements. CLGS solar cells, as a function of temperature, showed drastic changes in n and E(a) in the space charge region (SCR) that forms near the ZnS/CIGS interface. Furthermore, by using a C-V measured substrate doping profiling method, we confirmed that the CIGS absorption layer had a graded band-gap structure from the end point of the SCR to the CIGS/Mo back contacts, while c-Si solar cells had a uniformly doped carrier concentration.