Self-heating hotspots in superconducting nanowires cooled by phonon black-body radiation.

Controlling thermal transport is important for a range of devices and technologies, from phase change memories to next-generation electronics. This is especially true in nano-scale devices where thermal transport is altered by the influence of surfaces and changes in dimensionality. In superconducting nanowire single-photon detectors, the thermal boundary conductance between the nanowire and the substrate it is fabricated on influences all of the performance metrics that make these detectors attractive for applications. This includes the maximum count rate, latency, jitter, and quantum efficiency. Despite its importance, the study of thermal boundary conductance in superconducting nanowire devices has not been done systematically, primarily due to the lack of a straightforward characterization method. Here, we show that simple electrical measurements can be used to estimate the thermal boundary conductance between nanowires and substrates and that these measurements agree with acoustic mismatch theory across a variety of substrates. Numerical simulations allow us to refine our understanding, however, open questions remain. This work should enable thermal engineering in superconducting nanowire electronics and cryogenic detectors for improved device performance.

Dual slot-mode NOEM phase shifter.

Photonic system component counts are increasing rapidly, particularly in CMOS-compatible silicon photonics processes. Large numbers of cascaded active photonic devices are difficult to implement when accounting for constraints on area, power dissipation, and response time. Plasma dispersion and the thermo-optic effect, both available in CMOS-compatible silicon processes, address a subset of these criteria. With the addition of a few back-end-of-line etch processing steps, silicon photonics platforms can support nano-opto-electro-mechanical (NOEM) phase shifters. Realizing NOEM phase shifters that operate at CMOS-compatible voltages (≤ 1.2 V) and with low insertion loss remains a challenge. Here, we introduce a novel NOEM phase shifter fabricated alongside 90 nanometer transistors that imparts 5.63 radians phase shift at 1.08 volts bias over an actuation length of 25µm with an insertion loss of less than 0.04 dB and 3 dB bandwidth of 0.26 MHz.

Cryogenic Memory Architecture Integrating Spin Hall Effect based Magnetic Memory and Superconductive Cryotron Devices.

One of the most challenging obstacles to realizing exascale computing is minimizing the energy consumption of L2 cache, main memory, and interconnects to that memory. For promising cryogenic computing schemes utilizing Josephson junction superconducting logic, this obstacle is exacerbated by the cryogenic system requirements that expose the technology's lack of high-density, high-speed and power-efficient memory. Here we demonstrate an array of cryogenic memory cells consisting of a non-volatile three-terminal magnetic tunnel junction element driven by the spin Hall effect, combined with a superconducting heater-cryotron bit-select element. The write energy of these memory elements is roughly 8 pJ with a bit-select element, designed to achieve a minimum overhead power consumption of about 30%. Individual magnetic memory cells measured at 4 K show reliable switching with write error rates below 10-6, and a 4 × 4 array can be fully addressed with bit select error rates of 10-6. This demonstration is a first step towards a full cryogenic memory architecture targeting energy and performance specifications appropriate for applications in superconducting high performance and quantum computing control systems, which require significant memory resources operating at 4 K.

Author Correction: Induced unconventional superconductivity on the surface states of Bi2Te3 topological insulator.

The original version of this Article contained an error in Fig. 6b. In the top scattering process, while the positioning of both arrows was correct, the colours were switched: the first arrow was red and the second arrow was blue, rather than the correct order of blue then red.

Author Correction: Induced unconventional superconductivity on the surface states of Bi2Te3 topological insulator.

The original version of this Article omitted the following from the Acknowledgements:"This work was partly supported by the Research Council of Norway through its Centres of Excellence funding scheme, project number 262633, QuSpin."This has now been corrected in both the PDF and HTML versions of the article.

Induced unconventional superconductivity on the surface states of Bi2Te3 topological insulator.

Topological superconductivity is central to a variety of novel phenomena involving the interplay between topologically ordered phases and broken-symmetry states. The key ingredient is an unconventional order parameter, with an orbital component containing a chiral p x + ip y wave term. Here we present phase-sensitive measurements, based on the quantum interference in nanoscale Josephson junctions, realized by using Bi2Te3 topological insulator. We demonstrate that the induced superconductivity is unconventional and consistent with a sign-changing order parameter, such as a chiral p x + ip y component. The magnetic field pattern of the junctions shows a dip at zero externally applied magnetic field, which is an incontrovertible signature of the simultaneous existence of 0 and π coupling within the junction, inherent to a non trivial order parameter phase. The nano-textured morphology of the Bi2Te3 flakes, and the dramatic role played by thermal strain are the surprising key factors for the display of an unconventional induced order parameter.