Classifying Single Channel Epileptic EEG data based on Sparse Representation using Shallow Autoencoder.

Patient independent epileptic seizure detection algorithm for scalp electroencephalogram (EEG) data is pro- posed in this paper. Principal motivation of this work is to integrate neural and conventional machine learning methods to develop a classification system which can advance the current wearable health systems in terms of computational complexity and accuracy. Being based on processing a single channel EEG processing, the approach is suitable for usage with small wireless sensors. A shallow autoencoder model is utilized for sparse representation of the EEG signal followed by k-nearest neighbor (kNN) classifier to categorize the data as epileptic or non-epileptic. Using a single EEG channel an optimum sparsity level is explored in the encoded sample. Attaining an accuracy, sensitivity and specificity of 98.85%, 99.29% and 98.86% respectively, for CHB-MIT scalp EEG database, proposed classification method outperforms state of- the-art seizure detection methodologies. Experiments has shown that this performance was possible by using a sparsity level of 4 in the auto-encoder. Furthermore, use of shallow learning instead of deep learning approach for generation of sparse but effective representation is computationally lighter than many other feature extraction and preprocessing methods.

Design and Implementation of an On-Chip Patient-Specific Closed-Loop Seizure Onset and Termination Detection System.

This paper presents the design of an area- and energy-efficient closed-loop machine learning-based patient-specific seizure onset and termination detection algorithm, and its on-chip hardware implementation. Application- and scenario-based tradeoffs are compared and reviewed for seizure detection and suppression algorithm and system which comprises electroencephalography (EEG) data acquisition, feature extraction, classification, and stimulation. Support vector machine achieves a good tradeoff among power, area, patient specificity, latency, and classification accuracy for long-term monitoring of patients with limited training seizure patterns. Design challenges of EEG data acquisition on a multichannel wearable environment for a patch-type sensor are also discussed in detail. Dual-detector architecture incorporates two area-efficient linear support vector machine classifiers along with a weight-and-average algorithm to target high sensitivity and good specificity at once. On-chip implementation issues for a patient-specific transcranial electrical stimulation are also discussed. The system design is verified using CHB-MIT EEG database [1] with a comprehensive measurement criteria which achieves high sensitivity and specificity of 95.1% and 96.2%, respectively, with a small latency of 1 s. It also achieves seizure onset and termination detection delay of 2.98 and 3.82 s, respectively, with seizure length estimation error of 4.07 s.

A 1.83 µJ/Classification, 8-Channel, Patient-Specific Epileptic Seizure Classification SoC Using a Non-Linear Support Vector Machine.

A non-linear support vector machine (NLSVM) seizure classification SoC with 8-channel EEG data acquisition and storage for epileptic patients is presented. The proposed SoC is the first work in literature that integrates a feature extraction (FE) engine, patient specific hardware-efficient NLSVM classification engine, 96 KB SRAM for EEG data storage and low-noise, high dynamic range readout circuits. To achieve on-chip integration of the NLSVM classification engine with minimum area and energy consumption, the FE engine utilizes time division multiplexing (TDM)-BPF architecture. The implemented log-linear Gaussian basis function (LL-GBF) NLSVM classifier exploits the linearization to achieve energy consumption of 0.39 µ J/operation and reduces the area by 28.2% compared to conventional GBF implementation. The readout circuits incorporate a chopper-stabilized DC servo loop to minimize the noise level elevation and achieve noise RTI of 0.81 µ Vrms for 0.5-100 Hz bandwidth with an NEF of 4.0. The 5 × 5 mm (2) SoC is implemented in a 0.18 µm 1P6M CMOS process consuming 1.83 µ J/classification for 8-channel operation. SoC verification has been done with the Children's Hospital Boston-MIT EEG database, as well as with a specific rapid eye-blink pattern detection test, which results in an average detection rate, average false alarm rate and latency of 95.1%, 0.94% (0.27 false alarms/hour) and 2 s, respectively.