Performance Analysis of Conventional Machine Learning Algorithms for Diabetic Sensorimotor Polyneuropathy Severity Classification.

BACKGROUND: Diabetic peripheral neuropathy (DSPN), a major form of diabetic neuropathy, is a complication that arises in long-term diabetic patients. Even though the application of machine learning (ML) in disease diagnosis is a very common and well-established field of research, its application in diabetic peripheral neuropathy (DSPN) diagnosis using composite scoring techniques like Michigan Neuropathy Screening Instrumentation (MNSI), is very limited in the existing literature. METHOD: In this study, the MNSI data were collected from the Epidemiology of Diabetes Interventions and Complications (EDIC) clinical trials. Two different datasets with different MNSI variable combinations based on the results from the eXtreme Gradient Boosting feature ranking technique were used to analyze the performance of eight different conventional ML algorithms. RESULTS: The random forest (RF) classifier outperformed other ML models for both datasets. However, all ML models showed almost perfect reliability based on Kappa statistics and a high correlation between the predicted output and actual class of the EDIC patients when all six MNSI variables were considered as inputs. CONCLUSIONS: This study suggests that the RF algorithm-based classifier using all MNSI variables can help to predict the DSPN severity which will help to enhance the medical facilities for diabetic patients.

A high-speed and low-offset dynamic latch comparator.

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 µm CMOS process show that the equivalent input-referred offset voltage is 720 µV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 µW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of 148.80 µm × 59.70 µm.