Electrical properties of GaSb/InAsSb core/shell nanowires.

Temperature dependent electronic properties of GaSb/InAsSb core/shell and GaSb nanowires have been studied. Results from two-probe and four-probe measurements are compared to distinguish between extrinsic (contact-related) and intrinsic (nanowire) properties. It is found that a thin (2-3 nm) InAsSb shell allows low barrier charge carrier injection to the GaSb core, and that the presence of the shell also improves intrinsic nanowire mobility and conductance in comparison to bare GaSb nanowires. Maximum intrinsic field effect mobilities of 200 and 42 cm(2) Vs(-1) were extracted for the GaSb/InAsSb core/shell and bare-GaSb NWs at room temperature, respectively. The temperature-dependence of the mobility suggests that ionized impurity scattering is the dominant scattering mechanism in bare GaSb while phonon scattering dominates in core/shell nanowires. Top-gated field effect transistors were fabricated based on radial GaSb/InAsSb heterostructure nanowires with shell thicknesses in the range 5-7 nm. The fabricated devices exhibited ambipolar conduction, where the output current was studied as a function of AC gate voltage and frequency. Frequency doubling was experimentally demonstrated up to 20 kHz. The maximum operating frequency was limited by parasitic capacitance associated with the measurement chip geometry.

Diameter-Dependent photocurrent in InAsSb nanowire infrared photodetectors.

Photoconductors using vertical arrays of InAs/InAs(1-x)Sb(x) nanowires with varying Sb composition x have been fabricated and characterized. The spectrally resolved photocurrents are strongly diameter dependent with peaks, which are red-shifted with diameter, appearing for thicker wires. Results from numerical simulations are in good agreement with the experimental data and reveal that the peaks are due to resonant modes that enhance the coupling of light into the wires. Through proper selection of wire diameter, the absorptance can be increased by more than 1 order of magnitude at a specific wavelength compared to a thin planar film with the same amount of material. A maximum 20% cutoff wavelength of 5.7 µm is obtained at 5 K for a wire diameter of 717 nm at a Sb content of x = 0.62, but simulations predict that detection at longer wavelengths can be achieved by increasing the diameter. Furthermore, photodetection in InAsSb nanowire arrays integrated on Si substrates is also demonstrated.

Diameter limitation in growth of III-Sb-containing nanowire heterostructures.

The nanowire geometry offers significant advantages for exploiting the potential of III-Sb materials. Strain due to lattice mismatch is efficiently accommodated, and carrier confinement effects can be utilized in tunneling and quantum devices for which the III-Sb materials are of particular interest. It has however proven difficult to grow thin (below a few tens of nanometers), epitaxial III-Sb nanowires, as commonly no growth is observed below some critical diameter. Here we explore the processes limiting the diameter of III-Sb nanowires in a model system, in order to develop procedures to control this effect. The InAs-GaSb heterostructure system was chosen due to its great potential for tunneling devices in future low-power electronics. We find that with increasing growth temperature or precursor partial pressures, the critical diameter for GaSb growth on InAs decreases. To explain this trend we propose a model where the Gibbs-Thomson effect limits the Sb supersaturation in the catalyst particle. This understanding enabled us to further reduce the nanowire diameter down to 32 nm for GaSb grown on 21 nm InAs stems. Finally, we show that growth conditions must be carefully optimized for these small diameters, since radial growth increases for increased precursor partial pressures beyond the critical values required for nucleation.

Single InAs/GaSb nanowire low-power CMOS inverter.

III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

Controlling the abruptness of axial heterojunctions in III-V nanowires: beyond the reservoir effect.

Heterostructure nanowires have many potential applications due to the avoidance of interface defects by lateral strain relaxation. However, most heterostructure semiconductor nanowires suffer from persistent interface compositional grading, normally attributed to the dissolution of growth species in the common alloy seed particles. Although progress has been made for some material systems, most binary material combinations remain problematic due to the interaction of growth species in the alloy. In this work we investigate the formation of interfaces in InAs-GaAs heterostructures experimentally and theoretically and demonstrate a technique to attain substantially sharper interfaces. We show that by pulsing the Ga source during heterojunction formation, In is pushed out before GaAs growth initiates, greatly reducing In carry-over. This procedure will be directly applicable to any nanowire system with finite nonideal solubility of growth species in the alloy seed particle and greatly improve the applicability of these structures in future devices.

Uniform and position-controlled InAs nanowires on 2" Si substrates for transistor applications.

This study presents a novel approach for indirect integration of InAs nanowires on 2'' Si substrates. We have investigated and developed epitaxial growth of InAs nanowires on 2'' Si substrates via the introduction of a thin yet high-quality InAs epitaxial layer grown by metalorganic vapor phase epitaxy. We demonstrate well-aligned nanowire growth including precise position and diameter control across the full wafer using very thin epitaxial layers (<300 nm). Statistical analysis results performed on the grown nanowires across the 2'' wafer size verifies our full control on the grown nanowire with 100% growth yield. From the crystallographic viewpoint, these InAs nanowires are predominantly of wurtzite structure. Furthermore, we show one possible device application of the aforementioned structure in vertical wrap-gated field-effect transistor geometry. The vertically aligned InAs nanowires are utilized as transistor channels and the InAs epitaxial layer is employed as the source contact. A high uniformity of the device characteristics for numerous transistors is further presented and RF characterization of these devices demonstrates an f(t) of 9.8 GHz.

High current density Esaki tunnel diodes based on GaSb-InAsSb heterostructure nanowires.

We present electrical characterization of broken gap GaSb-InAsSb nanowire heterojunctions. Esaki diode characteristics with maximum reverse current of 1750 kA/cm(2) at 0.50 V, maximum peak current of 67 kA/cm(2) at 0.11 V, and peak-to-valley ratio (PVR) of 2.1 are obtained at room temperature. The reverse current density is comparable to that of state-of-the-art tunnel diodes based on heavily doped p-n junctions. However, the GaSb-InAsSb diodes investigated in this work do not rely on heavy doping, which permits studies of transport mechanisms in simple transistor structures processed with high-κ gate dielectrics and top-gates. Such processing results in devices with improved PVR (3.5) and stability of the electrical properties.

InAs/GaSb heterostructure nanowires for tunnel field-effect transistors.

InAs/GaSb nanowire heterostructures with thin GaInAs inserts were grown by MOVPE and characterized by electrical measurements and transmission electron microscopy. Down-scaling of the insert thickness was limited because of an observed sensitivity of GaSb nanowire growth to the presence of In. By employing growth interrupts in between the InAs and GaInAs growth steps it was possible to reach an insert thickness down to 25 nm. Two-terminal devices show a diode behavior, where temperature-dependent measurements indicate a heterostructure barrier height of 0.5 eV, which is identified as the valence band offset between the InAs and GaSb. Three-terminal transistor structures with a top-gate positioned at the heterointerface show clear indications of band-to-band tunnelling.