ABSTRACT
Perovskite quantum dots (PQDs) have many properties that make them attractive for optoelectronic applications, including expanded compositional tunability and crystallographic stabilization. While they have not achieved the same photovoltaic (PV) efficiencies of top-performing perovskite thin films, they do reproducibly show high open circuit voltage (VOC) in comparison. Further understanding of the VOC attainable in PQDs as a function of surface passivation, contact layers, and PQD composition will further progress the field and may lend useful lessons for non-QD perovskite solar cells. Here, we use photoluminescence-based spectroscopic techniques to understand and identify the governing physics of the VOC in CsPbI3 PQDs. In particular, we probe the effect of the ligand exchange and contact interfaces on the VOC and free charge carrier concentration. The free charge carrier concentration is orders of magnitude higher than in typical perovskite thin films and could be tunable through ligand chemistry. Tuning the PQD A-site cation composition via replacement of Cs+ with FA+ maintains the background carrier concentration but reduces the trap density by up to a factor of 40, reducing the VOC deficit. These results dictate how to improve PQD optoelectronic properties and PV device performance and explain the reduced interfacial recombination observed by coupling PQDs with thin-film perovskites for a hybrid absorber layer.
ABSTRACT
Developments in photovoltaic device architectures are necessary to make solar energy a cost-effective and reliable source of renewable energy amidst growing global energy demands and climate change. Thin film CdTe technology has demonstrated cost-competitiveness and increasing efficiencies due partially to rapid fabrication times, minimal material usage, and introduction of a CdSeTe alloy into a ~3 µm absorber layer. This work presents the close-space sublimation fabrication of thin, 1.5 µm CdSeTe/CdTe bilayer devices using an automated in-line vacuum deposition system. The thin bilayer structure and fabrication technique minimize deposition time, increase device efficiency, and facilitate future thin absorber-based device architecture development. Three fabrication parameters appear to be the most impactful for optimizing thin CdSeTe/CdTe absorber devices: substrate preheat temperature, CdSeTe:CdTe thickness ratio, and CdCl2 passivation. For proper sublimation of the CdSeTe, the substrate temperature prior to deposition must be ~540 °C (higher than that for CdTe) as controlled by dwell time in a preheat source. Variation in the CdSeTe:CdTe thickness ratio reveals a strong dependence of device performance on this ratio. The optimal absorber thicknesses are 0.5 µm CdSeTe/1.0 µm CdTe, and non-optimized thickness ratios reduce efficiency through back-barrier effects. Thin absorbers are sensitive to CdCl2 passivation variation; a much less aggressive CdCl2 treatment (compared to thicker absorbers) regarding both temperature and time yields optimal device performance. With optimized fabrication conditions, CdSeTe/CdTe increases device short-circuit current density and photoluminescence intensity compared to single-absorber CdTe. Additionally, an in-line close-space sublimation vacuum deposition system offers material and time reduction, scalability, and attainability of future ultra-thin absorber architectures.
