ABSTRACT
Flexible displays on a polyimide (PI) substrate are widely regarded as a promising next-generation display technology due to their versatility in various applications. Among other bendable materials used as display panel substrates, PI is especially suitable for flexible displays for its high glass transition temperature and low coefficient of thermal expansion. PI cured under various temperatures (260 °C, 360 °C, and 460 °C) was implemented in metal-insulator-metal (MIM) capacitors, amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFT), and actual display panels to analyze device stability and panel product characteristics. Through electrical analysis of the MIM capacitor, it was confirmed that the charging effect in the PI substrates intensified as the PI curing temperature increased. The threshold voltage shift (ΔVth) of the samples was found to increase with rising curing temperature under negative bias temperature stress (NBTS) due to the charging effect. Our analyses also show that increasing ΔVth exacerbates the image sticking phenomenon observed in display panels. These findings ultimately present a direct correlation between the curing temperature of polyimide substrates and the panel image sticking phenomenon, which could provide an insight into the improvement of future PI-substrate-based displays.
ABSTRACT
In this study, three different crystalline states of silicon were prepared to be doped with phosphorous by IMD, amorphous, poly crystalline and single crystalline silicon. The dose was controlled by IMD duration time and heat treatment for electrical activation was done in RTA and Furnace. In case of RTA, annealing temperature was controlled by the duration time of power application. In case of a single crystal substrate, the resistance was measured to be 20-50 omega/square depending on the dose and annealing temperature. In case of poly crystal, we could observe segregation of the dopant at grain boundaries, which caused increase of the resistance with increase of annealing temperature. In case of amorphous silicon thin film, this phenomenon could not be observed due to lack of the grain boundaries and the minimum resistance of this work was about 300 omega/square, which was about the same to that in a poly silicon thin film.
ABSTRACT
A Lightly Doped Drain (LDD) structure is known to be very effective in preventing hot electrons in modern NMOS transistors. In this work, the lightly doped region was formed in poly TFT by using a separate LDD mask aligned to a gate mask. The misalignment can be calculated to be about 1.5 microm, and depending on the location of the V(d) application between the source and drain, an LDD or Lightly Doped Source (LDS) structure can be realized on the same TFT. In this way, we can make a perfect comparison between these two structures. It turned out that the LDD is mainly responsible for the low leakage current, and no more than 0.5 microm of the lightly doped region is necessary to lower the leakage current down to less than 5 x 10(-11) amps at V(d) = 10 volts. Typically, the on-current of MILC TFT is more than 10(-4) amps, but 2.5 microm LDS decreases it to below 10(-7) amps.
