ABSTRACT
A good approximation to power amplifier (PA) behavioral modeling requires precise baseband models to mitigate nonlinearities. Since digital predistortion (DPD) is used to provide the PA linearization, a framework is necessary to validate the modeling figures of merit support under signal conditioning and transmission restrictions. A field-programmable gate array (FPGA)-based testbed is developed to measure the wide-band PA behavior using a single-carrier 64-quadrature amplitude modulation (QAM) multiplexed by orthogonal frequency-division multiplexing (OFDM) based on long-term evolution (LTE) as a stimulus, with different bandwidths signals. In the search to provide a heuristic target approach modeling, this paper introduces a feature extraction concept to find an appropriate complexity solution considering the high sparse data issue in amplitude to amplitude (AM-AM) and amplitude to phase AM-PM models extraction, whose penalties are associated with overfitting and hardware complexity in resulting functions. Thus, experimental results highlight the model performance for a high sparse data regime and are compared with a regression tree (RT), random forest (RF), and cubic-spline (CS) model accuracy capabilities for the signal conditioning to show a reliable validation, low-complexity, according to the peak-to-average power ratio (PAPR), complementary cumulative distribution function (CCDF), coefficients extraction, normalized mean square error (NMSE), and execution time figures of merit. The presented models provide a comparison with original data that aid to compare the dimension and robustness for each surrogate model where (i) machine learning (ML)-based and (ii) CS interpolate-based where high sparse data are present, NMSE between the CS interpolated based are also compared to demonstrate the efficacy in the prediction methods with lower convergence times and complexities.
Subject(s)
Amplifiers, Electronic , Equipment DesignABSTRACT
The signal conditioning treatment to achieve good relation of power with radio-frequency (RF) conversion in conventional transceiver systems require precise baseband models. A developed framework is built to provide a demonstration of the modeling figures of merit with orthogonal frequency division multiplexing (OFDM) support under signal conditioning and transmission restrictions to waveforms with high peak to average power ratio (PAPR) in practical applications. Therefore, peak and average power levels have to be limited to correct high PAPR for a better suited correction power from the amplifier that can lead to compression or clipping in the signal of interest. This work presents an alternative joint crest factor reduction (CFR) algorithm to correct the performance of PAPR. A real-time field-programmable gate array (FPGA) testbed is developed to characterize and measure the behavior of an amplifier using a single-carrier 64-QAM OFDM based on long-term evolution (LTE) downlink at 2.40 GHz as stimulus, across wide modulation bandwidths. The results demonstrate that the CFR accuracy capabilities for the signal conditioning show a reliable clipping reduction to give a smooth version of the clipping signal and provide a factor of correction for the unwanted out-of-band emission validated according to the adjacent channel power ratio (ACPR), PAPR, peak power, complementary cumulative distribution function (CCDF), and error vector magnitude (EVM) figures of merit.
ABSTRACT
The design of a remotely operated vehicle (ROV) with a size of 18.41 cm × 29.50 cm × 33.50 cm, and a weight of 15.64 kg, is introduced herein. The main goal is to capture underwater video by remote control communication in real time via Ethernet protocol. The ROV moves under the six brushless motors governed through a smart PID controller (Proportional + Integral + Derivative) and by using pulse-wide modulation with short pulses of 1 µs to improve the stability of the position in relation to the translational, ascent or descent, and rotational movements on three axes to capture images of 800 × 640 pixels on a video graphic array standard. The motion control, 3D position, temperature sensing, and video capture are performed at the same time, exploiting the four cores of the Raspberry Pi 3, using the threading library for parallel computing. In such a way, experimental results show that the video capture stage can process up to 42 frames per second on a Raspberry Pi 3. The remote control of the ROV is executed under a graphical user interface developed in Python, which is suitable for different operating systems, such as GNU/Linux, Windows, Android, and OS X. The proposed ROV can reach up to 100 m underwater, thus solving the issue of divers who can only reach 30 m depth. In addition, the proposed ROV can be useful in underwater applications such as surveillance, operations, maintenance, and measurement.
ABSTRACT
Profiling and parallel computing techniques in a cluster of six embedded systems with multiprocessors are introduced herein to implement a chaotic cryptosystem for digital color images. The proposed encryption method is based on stream encryption using a pseudo-random number generator with high-precision arithmetic and data processing in parallel with collective communication. The profiling and parallel computing techniques allow discovery of the optimal number of processors that are necessary to improve the efficiency of the cryptosystem. That is, the processing speed improves the time for generating chaotic sequences and execution of the encryption algorithm. In addition, the high numerical precision reduces the digital degradation in a chaotic system and increases the security levels of the cryptosystem. The security analysis confirms that the proposed cryptosystem is secure and robust against different attacks that have been widely reported in the literature. Accordingly, we highlight that the proposed encryption method is potentially feasible to be implemented in practical applications, such as modern telecommunication devices employing multiprocessors, e.g., smart phones, tablets, and in any embedded system with multi-core hardware.
