A CMOS Microelectrode Array System With Reconfigurable Sub-Array Multiplexing Architecture Integrating 24,320 Electrodes and 380 Readout Channels.

This article presents a CMOS microelectrode array (MEA) system with a reconfigurable sub-array multiplexing architecture using the time-division multiplexing (TDM) technique. The system consists of 24,320 TiN electrodes with 17.7 µm-pitch pixels and 380 column-parallel readout channels including a low-noise amplifier, a programmable gain amplifier, and a 10-b successive approximation register analog to digital converter. Readout channels are placed outside the pixel for high spatial resolution, and a flexible structure to acquire neural signals from electrodes selected by configuring in-pixel memory is realized. In this structure, a single channel can handle 8 to 32 electrodes, guaranteeing a temporal resolution from 5 kS/s to 20 kS/s for each electrode. A 128 × 190 MEA system was fabricated in a 110-nm CMOS process, and each readout channel consumes 81 µW at 1.5-V supply voltage featuring input-referred noise of 1.48 µVrms without multiplexing and 5.4 µVrms with multiplexing at the action-potential band (300 Hz-10 kHz).

A Sub- µW/Ch Analog Front-End for ∆-Neural Recording With Spike-Driven Data Compression.

We present a fully implantable neural recording IC with a spike-driven data compression scheme to improve the power efficiency and preserve crucial data for monitoring brain activities. A difference between two consecutive neural signals, ∆-neural signal, is sampled in each channel to reduce the full dynamic range and the required resolution of an analog-to-digital converter (ADC), enabling the whole analog chain to be operated at a 0.5-V supply. A set of multiple ∆-signals are stored in analog memory to extract the magnitude and frequency features of the incoming neural signals, which are utilized to discriminate spikes in these signals instantaneously after the acquisition in the analog domain. The energy- and area-efficient successive approximation ADC is implemented and only converts detected spikes, decreasing the power dissipation and the amount of neural data. A prototype 16-channel neural interface IC was fabricated using a 0.18-µm CMOS process, and each component in the analog front-end was fully characterized. We successfully demonstrated precise spike detection through both in vitro and in vivo acquisition of the neural signal. The prototype chip consumed 0.88 µW/channel at a 0.5-V supply for the recording and compressed about 89% of neural data, saving the power consumption and bandwidth in the system.