Bioinspired In-Sensor Multimodal Fusion for Enhanced Spatial and Spatiotemporal Association.

Multimodal perception can capture more precise and comprehensive information compared with unimodal approaches. However, current sensory systems typically merge multimodal signals at computing terminals following parallel processing and transmission, which results in the potential loss of spatial association information and requires time stamps to maintain temporal coherence for time-series data. Here we demonstrate bioinspired in-sensor multimodal fusion, which effectively enhances comprehensive perception and reduces the level of data transfer between sensory terminal and computation units. By adopting floating gate phototransistors with reconfigurable photoresponse plasticity, we realize the agile spatial and spatiotemporal fusion under nonvolatile and volatile photoresponse modes. To realize an optimal spatial estimation, we integrate spatial information from visual-tactile signals. For dynamic events, we capture and fuse in real time spatiotemporal information from visual-audio signals, realizing a dance-music synchronization recognition task without a time-stamping process. This in-sensor multimodal fusion approach provides the potential to simplify the multimodal integration system, extending the in-sensor computing paradigm.

Ultraflexible Monolithic Three-Dimensional Static Random Access Memory.

Flexible static random access memory (SRAM) plays an important role in flexible electronics and systems. However, achieving SRAM with a small footprint, high flexibility, and high thermal stability has always been a big challenge. In this work, an ultraflexible six-transistor SRAM with high integration density is realized based on a monolithic three-dimensional (M3D) design. In this design, vertical stacked n-type indium gallium zinc oxide thin film transistors and p-type carbon nanotube transistors share common gate and drain electrodes, respectively, saving interlayer vias used in traditional M3D designs. This compact architecture reduces the footprint of the SRAM cell from a six-transistor to a four-transistor area, saving 33% of the area, and significantly enables the SRAM to have the highest flexibility among the reported ones, withstanding a harsh deforming process (6000 cycles of bending at a radius of 500 µm) without performance degradation. Moreover, this design facilitates the thermal stability of the SRAM under high temperature (333 K). It also exhibits great static and dynamic performance, with the highest normalized hold noise margin of 73.6%, a maximum gain of 151.2, and a minimum static power consumption of 3.15 µW in hold operation among the reported flexible SRAMs. This demonstration provides possibilities for SRAMs to be used in advanced wearable system applications.

Intercoupling of Cascaded Metasurfaces for Broadband Spectral Scalability.

Electromagnetic metasurfaces have been intensively used as ultra-compact and easy-to-integrate platforms for versatile wave manipulations from optical to terahertz (THz) and millimeter wave (MMW) ranges. In this paper, the less investigated effects of the interlayer coupling of multiple metasurfaces cascaded in parallel are intensively exploited and leveraged for scalable broadband spectral regulations. The hybridized resonant modes of cascaded metasurfaces with interlayer couplings are well interpreted and simply modeled by the transmission line lumped equivalent circuits, which are used in return to guide the design of the tunable spectral response. In particular, the interlayer gaps and other parameters of double or triple metasurfaces are deliberately leveraged to tune the inter-couplings for as-required spectral properties, i.e., the bandwidth scaling and central frequency shift. As a proof of concept, the scalable broadband transmissive spectra are demonstrated in the millimeter wave (MMW) range by cascading multilayers of metasurfaces sandwiched together in parallel with low-loss dielectrics (Rogers 3003). Finally, both the numerical and experimental results confirm the effectiveness of our cascaded model of multiple metasurfaces for broadband spectral tuning from a narrow band centered at 50 GHz to a broadened range of 40~55 GHz with ideal side steepness, respectively.

Ultra-thin gate insulator of atomic-layer-deposited AlOxand HfOxfor amorphous InGaZnO thin-film transistors.

To strengthen the downscaling potential of top-gate amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), the ultra-thin gate insulator (GI) was comparatively implemented using the atomic-layer-deposited (ALD) AlOxand HfOx. Both kinds of high-kGIs exhibit good insulating properties even with the physical thickness thinning to 4 nm. Compared to the amorphous indium-gallium-zinc oxide (a-IGZO) TFTs with 4 nm AlOxGI, the 4 nm HfOxenables a larger GI capacitance, while the HfOx-gated TFT suffers higher gate leakage current and poorer subthreshold slope, respectively originating from the inherently small band offset and the highly defective interface between a-IGZO and HfOx. Such imperfect a-IGZO/HfOxinterface further causes noticeable positive bias stress instability. Both ALD AlOxand HfOxwere found to react with the underneath a-IGZO channel to generate the interface defects, such as metal interstitials and oxygen vacancies, while the ALD process of HfOxgives rise to a more severe reduction of a-IGZO. Moreover, when such a defective interface is covered by the top gate, it cannot be readily restored using the conventional oxidizing post-treatments and thus desires the reduction-resistant pre-treatments of AOSs.

Near-Ideal Top-Gate Controllability of InGaZnO Thin-Film Transistors by Suppressing Interface Defects with an Ultrathin Atomic Layer Deposited Gate Insulator.

An ultrathin atomic-layer-deposited (ALD) AlOx gate insulator (GI) was implemented for self-aligned top-gate (SATG) amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). Although the 4.0-nm thick AlOx exhibited ideal insulating properties, the interaction between ALD AlOx and predeposited a-IGZO caused a relatively defective interface, thus giving rise to hysteresis and bias stress instabilities. As analyzed using high-resolution transmission electron microscopy, X-ray photoelectron spectroscopy, and the Hall measurement, the chemical reaction between the ALD precursor and a-IGZO is revealed. This was effectively prevented by preoxidizing a-IGZO with nitrous oxide (N2O) plasma. With 4 nm-AlOx GI and low-defect interfaces, high performance and stability were simultaneously achieved on SATG a-IGZO TFTs, including a near-ideal record-low subthreshold swing of 60.8 mV/dec, a low operation voltage below 0.4 V, a moderate mobility of 13.3 cm2/V·s, a low off-current below 10-13 A, a large on/off ratio over 109, and negligible threshold-voltage shifts less than 0.04 V against various bias-temperature stresses. This work clarifies the vital interfacial reaction between top-gate high-k dielectrics and amorphous oxide semiconductors (AOSs) and further provides a feasible way to remove this obstacle to downscaling SATG AOS TFTs.

Transferred metal gate to 2D semiconductors for sub-1 V operation and near ideal subthreshold slope.

Ultrathin two-dimensional (2D) semiconductors are regarded as a potential channel material for low-power transistors with small subthreshold swing and low leakage current. However, their dangling bond­free surface makes it extremely difficult to deposit gate dielectrics with high-quality interface in metal-oxide-semiconductor (MOS) field-effect transistors (FETs). Here, we demonstrate a low-temperature process to transfer metal gate to 2D MoS2 for high-quality interface. By excluding extrinsic doping to MoS2 and increasing contact distance, the high­barrier height Pt-MoS2 Schottky junction replaces the commonly used MOS capacitor and eliminates the use of gate dielectrics. The MoS2 transferred metal gate (TMG) FETs exhibit sub-1 V operation voltage and a subthreshold slope close to thermal limit (60 mV/dec), owing to intrinsically high junction capacitance and the high-quality interface. The TMG and back gate enable logic functions in a single transistor with small footprint.

Low-temperature grown vertically aligned carbon nanotube array for an optimal infrared bolometer.

Vertically aligned carbon nanotube (VACNT) arrays have been explored as an absorber of thermal-type photodetectors. A long and dense VACNT array absorbs a wide spectral range of incident light with high absorption rate, but has a high thermal mass that results in a low response speed. To achieve a small thermal mass, a shorter and less dense VACNT array is needed. In addition, the high temperature needed to grow the VACNTs is detrimental to the functional sensing materials of the photodetector. The height, density, and growth temperature of VACNTs need to be optimized to achieve a working absorber that has high absorption rate and a high response speed. In this work, a low-temperature plasma enhanced chemical vapor deposition process is used to prepare various VACNT arrays with different heights and densities by controlling the CNT growth parameters. The absorption coefficients of the resulting samples are measured with Fourier transform infrared spectroscopy. An effective medium theory (EMT) is adopted to establish a working model of the VACNTs. Using experimentally extracted CNT density and height as fitting parameters, the EMT model is fitted to obtain theoretical absorption coefficients, which are found to be comparable to the experimentally measured absorption coefficients. Our experimental and theoretical investigations pave the way for future studies to integrate CNTs with infrared photodetectors.

Hybrid memristor-CMOS neurons for in-situ learning in fully hardware memristive spiking neural networks.

Spiking neural network, inspired by the human brain, consisting of spiking neurons and plastic synapses, is a promising solution for highly efficient data processing in neuromorphic computing. Recently, memristor-based neurons and synapses are becoming intriguing candidates to build spiking neural networks in hardware, owing to the close resemblance between their device dynamics and the biological counterparts. However, the functionalities of memristor-based neurons are currently very limited, and a hardware demonstration of fully memristor-based spiking neural networks supporting in-situ learning is very challenging. Here, a hybrid spiking neuron combining a memristor with simple digital circuits is designed and implemented in hardware to enhance neuron functions. The hybrid neuron with memristive dynamics not only realizes the basic leaky integrate-and-fire neuron function but also enables the in-situ tuning of the connected synaptic weights. Finally, a fully hardware spiking neural network with the hybrid neurons and memristive synapses is experimentally demonstrated for the first time, and in-situ Hebbian learning is achieved with this network. This work opens up a way towards the implementation of spiking neurons, supporting in-situ learning for future neuromorphic computing systems.

Synthesis of Vertical Carbon Nanotube Interconnect Structures Using CMOS-Compatible Catalysts.

Synthesis of the vertically aligned carbon nanotubes (CNTs) using complementary metal-oxide-semiconductor (CMOS)-compatible methods is essential to integrate the CNT contact and interconnect to nanoscale devices and ultra-dense integrated nanoelectronics. However, the synthesis of high-density CNT array at low-temperature remains a challenging task. The advances in the low-temperature synthesis of high-density vertical CNT structures using CMOS-compatible methods are reviewed. Primarily, recent works on theoretical simulations and experimental characterizations of CNT growth emphasized the critical roles of catalyst design in reducing synthesis temperature and increasing CNT density. In particular, the approach of using multilayer catalyst film to generate the alloyed catalyst nanoparticle was found competent to improve the active catalyst nanoparticle formation and reduce the CNT growth temperature. With the multilayer catalyst, CNT arrays were directly grown on metals, oxides, and 2D materials. Moreover, the relations among the catalyst film thickness, CNT diameter, and wall number were surveyed, which provided potential strategies to control the tube density and the wall density of synthesized CNT array.

Bistable active spectral tuning of one-dimensional nanophotonic crystal by phase change.

Active spectral tuning of nanophotonic devices offers many fascinating prospects for the realization of novel optical function. Here, switchable spectral response is enabled by the architecture of one-dimensional (1D) photonic crystal (PC) integrated with phase change material of the germanium antimony telluride (GST). Active and precise tuning of the bistable passband and central resonant frequency is demonstrated in the 1D PC composed of alternate SiN and GST nanofilms. An analytical model is derived to specify the tunable spectral features, including the band gap and resonant frequencies. Both the measured and calculated results show distinct red shifts of passband and the resonant minima (or maxima), well confirming theoretical predictions. This work demonstrates a route to construct active photonic devices with the electrically or thermally tunable spectra via 1D PC and potentially extends diverse applications based on the PC platform.

Sensing-range-tunable pressure sensors realized by self-patterned-spacer design and vertical CNT arrays embedded in PDMS.

A pressure sensor design suitable for a broad sensing range with high sensitivity and good stability is highly desirable for the detection of various pressures and meeting the requirements of different applications. Herein, we report sensing-range-tunable piezoresistive pressure sensors realized by self-patterned-spacer design. In the sensors, the two CNT-array layers embedded in PDMS are separated by the proposed self-patterned spacer. With this structure, the realized sensors with large initial resistance designed show tunable response thresholds from 300 Pa to 6.5 kPa while maintaining high sensitivity, which are realized by controlling the spacer thickness and the CNT length. Besides, the vertical CNT arrays have a large specific surface area, which can dramatically change the resistance of the pressure sensors and lead to high sensitivity with nearly 50 kPa-1. Benefiting from the designs of the self-patterned spacer and the advantageous combination of CNTs and PDMS, the pressure sensors also exhibit a rapid response/relaxation time of 24/32 ms, and good long-term stability with durability test over 10 000 loading/unloading cycles. On the other hand, the realized pressure sensors with small initial resistance designed show a typical piezoresistive characteristic. For applications, the pressure sensors with large initial resistance designed are suitable for the anti-noise applications with pressure thresholds to filter unnecessary noise and save power consumption, while the pressure sensors with small initial resistance designed show the capability of detecting mechanical forces and monitoring human physiological signals. Moreover, the self-patterned design and fabrication method of the spacers also show potentials to be applied in the existing works to further enhance or adjust the performance of those pressure sensors, showing great flexibility. This design demonstrates great potentials to be applied in future advanced flexible wearable systems such as health monitoring, human-machine interaction and the Internet of Things.

Low Temperature Synthesis of High-Density Carbon Nanotubes on Insulating Substrate.

A method to synthesize high-density, vertically-aligned, multi-wall carbon nanotubes (MWCNTs) on an insulating substrate at low temperature using a complementary metal⁻oxide⁻semiconductor (CMOS) compatible process is presented. Two factors are identified to be important in the carbon nanotube (CNT) growth, which are the catalyst design and the substrate material. By using a Ni⁻Al⁻Ni multilayer catalyst film and a ZrO2 substrate, vertically-aligned CNTs can be synthesized at 340 °C using plasma-enhanced chemical vapor deposition (PECVD). Both the quality and density of the CNTs can be enhanced by increasing the synthesis temperature. The function of the aluminum interlayer in reducing the activation energy of the CNT formation is studied. The nanoparticle sintering and quick accumulation of amorphous carbon covering the catalyst can prematurely stop CNT synthesis. Both effects can be suppressed by using a substrate with a high surface energy such as ZrO2.

Synthesis and interface characterization of CNTs on graphene.

Carbon nanotubes (CNTs) and graphene are potential candidates for future interconnect materials. CNTs are promising on-chip via interconnect materials due to their readily formed vertical structures, their current-carrying capacity, which is much larger than existing on-chip interconnect materials such as copper and tungsten, and their demonstrated ability to grow in patterned vias with sub-50 nm widths; meanwhile, graphene is suitable for horizontal interconnects. However, they both present the challenge of having high-resistance contacts with other conductors. An all-carbon structure is proposed in this paper, which can be formed using the same chemical vapor deposition method for both CNTs and graphene. Vertically aligned CNTs are grown directly on graphene with an Fe or Ni catalyst. The structural characteristics of the graphene and the grown CNTs are analyzed using Raman spectroscopy and electron microscopy techniques. The CNT-graphene interface is studied in detail using transmission electron microscopic analysis of the CNT-graphene heterostructure, which suggests C-C bonding between the two materials. Electrical measurement results confirm the existence of both a lateral conduction path within graphene and a vertical conduction path in the CNT-graphene heterostructure, giving further support to the C-C bonding at the CNT-graphene interface and resulting in potential applications for all-carbon interconnects.

A 200-Channel Area-Power-Efficient Chemical and Electrical Dual-Mode Acquisition IC for the Study of Neurodegenerative Diseases.

Microelectrode array (MEA) can be used in the study of neurodegenerative diseases by monitoring the chemical neurotransmitter release and the electrical potential simultaneously at the cellular level. Currently, the MEA technology is migrating to more electrodes and higher electrode density, which raises power and area constraints on the design of acquisition IC. In this paper, we report the design of a 200-channel dual-mode acquisition IC with highly efficient usage of power and area. Under the constraints of target noise and fast settling, the current channel design saves power by including a novel current buffer biased in discrete time (DT) before the TIA (transimpedance amplifier). The 200 channels are sampled at 20 kS/s and quantized by column-wise SAR ADCs. The prototype IC was fabricated in a 0.18 µm CMOS process. Silicon measurements show the current channel has 21.6 pArms noise with cyclic voltammetry (CV) and 0.48 pArms noise with constant amperometry (CA) while consuming 12.1 µW . The voltage channel has 4.07 µVrms noise in the bandwidth of 100 kHz and 0.2% nonlinearity while consuming 9.1 µW. Each channel occupies 0.03 mm(2) area, which is among the smallest.

Low voltage and high ON/OFF ratio field-effect transistors based on CVD MoS2 and ultra high-k gate dielectric PZT.

MoS2 and other atomic-level thick layered materials have been shown to have a high potential for outperforming Si transistors at the scaling limit. In this work, we demonstrate a MoS2 transistor with a low voltage and high ON/OFF ratio. A record small equivalent oxide thickness of ∼1.1 nm has been obtained by using ultra high-k gate dielectric Pb(Zr0.52Ti0.48)O3. The low threshold voltage (<0.5 V) is comparable to that of the liquid/gel gated MoS2 transistor. The small sub-threshold swing of 85.9 mV dec(-1), the high ON/OFF ratio of ∼10(8) and the negligible hysteresis ensure a high performance of the MoS2 transistor operating at 1 V. The extracted field-effect mobility of 1-10 cm(2) V(-1) s(-1) suggests a high crystalline quality of the CVD-grown MoS2 flakes. The combination of the two-dimensional layered semiconductor and the ultra high-k dielectric may enable the development of low-power electronic applications.

Highly aligned graphene/polymer nanocomposites with excellent dielectric properties for high-performance electromagnetic interference shielding.

Nanocomposites that contain reinforcements with preferred orientation have attracted significant attention because of their promising applications in a wide range of multifunctional fields. Many efforts have recently been focused on developing facile methods for preparing aligned graphene sheets in solvents and polymers because of their fascinating properties including liquid crystallinity and highly anisotropic characteristics. Self-aligned in situ reduced graphene oxide (rGO)/polymer nanocomposites are prepared using an all aqueous casting method. A remarkably low percolation threshold of 0.12 vol% is achieved in the rGO/epoxy system owing to the uniformly dispersed, monolayer graphene sheets with extremely high aspect ratios (>30000). The self-alignment into a layered structure at above a critical filler content induces a unique anisotropy in electrical and mechanical properties due to the preferential formation of conductive and reinforcing networks along the alignment direction. Accompanied by the anisotropic electrical conductivities are exceptionally high dielectric constants of over 14000 with 3 wt% of rGO at 1 kHz due to the charge accumulation at the highly-aligned conductive filler/insulating polymer interface according to the Maxwell-Wagner-Sillars polarization principle. The highly dielectric rGO/epoxy nanocomposites with the engineered structure and properties present high performance electromagnetic interference shielding with a remarkable shilding efficiency of 38 dB.

The use of SU-8 topographically guided microelectrode array in measuring extracellular field potential propagation.

The microelectrode array (MEA) can be used to study extracellular field potentials (exFPs) of electrogenic cells. Microcontact printing, which must be repeated after each experiment, is often used to promote accurate positioning of cells onto electrodes. The present study used MEAs with evenly spaced detection electrodes aligning along permanent SU-8 topographical guidance channels to measure propagation direction and speed. Chronotropic agents, isoproterenol (ISO, 1 nM-1 mM), and verapamil (VP, 1 nM-10 µM); and potassium channel openers (KCOs), pinacidil (PIN), and SDZ PCO400 (SDZ), were used to characterize these MEA chips. ISO (1 mM) enhanced the propagation speed from 247.25 ± 50.58 µm/ms 381.29 ± 92.01 µm/ms (n = 9, p < 0.05), whereas VP (10 µM) reduced the propagation speed completely (n = 12, p < 0.001). PIN (1 mM) significantly reduced the propagation speed from 278.6 ± 43.7 µm/ms to 49.7 ± 27.7 µm/ms (n = 10, p < 0.001), whereas SDZ (1 mM) completely stopped the propagation (n = 9, p < 0.001). Both KCOs induced conduction pattern changes similar to those observed in cardiac arrhythmia. The MEA chips with SU-8 guidance channels may be used to study cardiovascular diseases that are related to conduction disruption.

Modeling of the cell-electrode interface noise for microelectrode arrays.

Microelectrodes are widely used in the physiological recording of cell field potentials. As microelectrode signals are generally in the µV range, characteristics of the cell-electrode interface are important to the recording accuracy. Although the impedance of the microelectrode-solution interface has been well studied and modeled in the past, no effective model has been experimentally verified to estimate the noise of the cell-electrode interface. Also in existing interface models, spectral information is largely disregarded. In this work, we developed a model for estimating the noise of the cell-electrode interface from interface impedances. This model improves over existing noise models by including the cell membrane capacitor and frequency dependent impedances. With low-noise experiment setups, this model is verified by microelectrode array (MEA) experiments with mouse muscle myoblast cells. Experiments show that the noise estimated from this model has <;10% error, which is much less than estimations from existing models. With this model, noise of the cell-electrode interface can be estimated by simply measuring interface impedances. This model also provides insights for micro- electrode design to achieve good recording signal-to-noise ratio.

A unified drain current model for nanoscale double-gate and surrounding-gate MOSFETs incorporating velocity saturation.

A unified drain current model for undoped or lightly doped symmetric double-gate and surrounding-gate MOSFETs incorporating velocity saturation effect is proposed in this paper. The unified charge-based core model for undoped or lightly doped double-gate and surrounding-gate MOSFETs is presented first based on the previously published separate models. Caughey-Thomas engineering mobility model with its exponent factor n = 2 is then integrated self-consistently into the unified drain current model development of the two device structures. Extensive two dimensional and three dimensional device simulations are performed to validate the proposed model. Good agreements of the output and transfer characteristics between the unified model and the numerical simulations are obtained for both the double-gate and surrounding-gate MOSFETs. Symmetry property of the proposed unified current model is obtained with the exponent factor n = 2 in Cauhey-Thomas Model.