ABSTRACT
This work studies the effect of post annealing of pentacene on a flexible substrate through the examination of electrical properties and surface morphologies. It is confirmed that the best performance of devices is achieved when the post annealing temperature is 60 degrees C, since the grain size increases, which decrease grain boundaries caused charge transport limit. We can also confirmed the large threshold voltage shift of device annealed at 60 degrees C that means the lower trap density between channel and insulator interface. The device annealed at 60 degrees C exhibits a saturation mobility of 1.99 cm2/V x s, an on/off ratio of 1.87 x 10(4), and a subthreshold slope of 2.5 V/decade.
Subject(s)
Electrodes , Membranes, Artificial , Nanostructures/chemistry , Naphthacenes/chemistry , Titanium/chemistry , Transistors, Electronic , Elastic Modulus , Electric Conductivity , Equipment Design , Equipment Failure Analysis , Hardness , Hot Temperature , Materials Testing , Nanostructures/ultrastructureABSTRACT
This paper describes the fabrication of pentacene thin-film transistors (TFTs) with an organic/inorganic hybrid gate dielectric, consisting of cross-linked poly(4-vinylphenol) (PVP) and Bi5Nb3O15. A 300-nm-thick Bi5Nb3O15 dielectric film, grown at room temperature, exhibits a high dielectric constant (high-k) value of 40 but has an undesirable interface with organic semiconductors (OSC). To form better interfaces with OSC, a cross-linked PVP dielectric was stacked on the Bi5Nb3O15 dielectric. It is shown that, with the introduction of a hybrid dielectric, our devices not only can be operated at a low voltage (- -5 V) but also have improved electrical characteristics and photoresponse, including a field-effect mobility of 0.72 cm2/V x s, current sub-threshold slopes of 0.29 V/decade, and a photoresponse of 4.84 at a gate bias V(G) = 0 V under 100 mW/cm2 AM 1.5 illumination.
