Distributed Nodes-Based Collaborative Sustaining of Precision Clock Synchronization Upon Master Clock Failure in IEEE 1588 System.

This paper proposes a distributed nodes-based clock synchronization method to sustain sub-microsecond precision synchronization of slave clocks upon master clock failure in IEEE 1588 PTP (precision time protocol) system. The sustaining is achieved by synchronizing the slave clocks to the estimated reference clock which is obtained from the analysis of distributed slave clocks. The proposed method consists of two clock correction functions (i.e., a self-correction and a collaborative correction, respectively). Upon master failure, the self-correction estimates a clock correction value based on the clock model which is constructed during normal PTP operation. The collaborative correction is performed in the preselected management node. The management node estimates a reference clock by collecting and analyzing clock information gathered from the other slave clocks. The performance of the proposed method is simulated by computer to show its usefulness. It is confirmed that the fifty (50) clock model-based collaborative correction maintains 10-6 second PTP accuracy for 10 min prolonged period after the master failure when tested with clock offset variations less than 50 ppm.

Improved Time-Synchronization Algorithm Based on Direct Compensation of Disturbance Effects.

In this paper, an improved time-synchronization algorithm is proposed. The improvement of time synchronizing performance was achieved by introducing a stochastic model-based direct compensation of the disturbance effects appearing in the IEEE 1588 Precision Time Protocol (PTP)-based time synchronization system. A dynamic model of PTP clock system was obtained by reflecting the three major sources of disturbances, i.e., clock frequency drift, clock rate offset, and network noise. With the application of the dynamic model of the PTP clock system, the effects of the disturbances can be effectively eliminated in the PTP time synchronization control loop. Computer simulations are performed to verify the performance of the proposed time synchronization algorithm by applying the various types of disturbances, including network noise and clock drift. The simulation results are compared with those of other representative time synchronization algorithms, i.e., IEEE 1588 PTP algorithm and Kalman-filter-based algorithm. It is shown that the proposed algorithm improves time synchronizing performance up to 84% with respect to that of the Kalman-filter-based synchronization algorithm when simulated with colored noise type disturbances. The proposed time synchronization algorithm is expected to contribute for the realization of future Ethernet-based industry-plant monitoring and control including IEC 61850-based digital substation.

The Effect of Time Synchronization Error in LAN-Based Digital Substation.

In this paper, the effect of time synchronization error on protection algorithms are studied for the usage of the LAN-based collaborative protection. In order to derive the effect of time synchronization, this paper proposes a substation model which is constructed with IEEE 1588 Precision Time Protocol (PTP) supported intelligent electronic devices. The proposed model is used as an example of a target platform to study the effect of time synchronization error with two typical substation protection algorithms, i.e., current differential-based substation protection and distance protection algorithms. From the analyzed and the simulated results, it was well observed that time synchronization error is a significant error-causing factor for both protection algorithms, resulting in erroneous detection of faults and erroneous estimation of fault distances, respectively. The results of research performed in this paper are expected to provide a good guide for constructing the future LAN-based digital power substation with precise time synchronization.

Segmentized Clear Channel Assessment for IEEE 802.15.4 Networks.

This paper proposed segmentized clear channel assessment (CCA) which increases the performance of IEEE 802.15.4 networks by improving carrier sense multiple access with collision avoidance (CSMA/CA). Improving CSMA/CA is important because the low-power consumption feature and throughput performance of IEEE 802.15.4 are greatly affected by CSMA/CA behavior. To improve the performance of CSMA/CA, this paper focused on increasing the chance to transmit a packet by assessing precise channel status. The previous method used in CCA, which is employed by CSMA/CA, assesses the channel by measuring the energy level of the channel. However, this method shows limited channel assessing behavior, which comes from simple threshold dependent channel busy evaluation. The proposed method solves this limited channel decision problem by dividing CCA into two groups. Two groups of CCA compare their energy levels to get precise channel status. To evaluate the performance of the segmentized CCA method, a Markov chain model has been developed. The validation of analytic results is confirmed by comparing them with simulation results. Additionally, simulation results show the proposed method is improving a maximum 8.76% of throughput and decreasing a maximum 3.9% of the average number of CCAs per packet transmission than the IEEE 802.15.4 CCA method.

Designing a ring-VCO for RFID transponders in 0.18 µm CMOS process.

In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 µm process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5-2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of -126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency.

High-speed current dq PI controller for vector controlled PMSM drive.

High-speed current controller for vector controlled permanent magnet synchronous motor (PMSM) is presented. The controller is developed based on modular design for faster calculation and uses fixed-point proportional-integral (PI) method for improved accuracy. Current dq controller is usually implemented in digital signal processor (DSP) based computer. However, DSP based solutions are reaching their physical limits, which are few microseconds. Besides, digital solutions suffer from high implementation cost. In this research, the overall controller is realizing in field programmable gate array (FPGA). FPGA implementation of the overall controlling algorithm will certainly trim down the execution time significantly to guarantee the steadiness of the motor. Agilent 16821A Logic Analyzer is employed to validate the result of the implemented design in FPGA. Experimental results indicate that the proposed current dq PI controller needs only 50 ns of execution time in 40 MHz clock, which is the lowest computational cycle for the era.