Cu-Based Thermocompression Bonding and Cu/Dielectric Hybrid Bonding for Three-Dimensional Integrated Circuits (3D ICs) Application.

Advanced packaging technology has become more and more important in the semiconductor industry because of the benefits of higher I/O density compared to conventional soldering technology. In advanced packaging technology, copper-copper (Cu-Cu) bonding has become the preferred choice due to its excellent electrical and thermal properties. However, one of the major challenges of Cu-Cu bonding is the high thermal budget of the bonding process caused by Cu oxidation, which can result in wafer warpage and other back-end-of-line process issues in some cases. Thus, for specific applications, reducing the thermal budget and preventing Cu oxidation are important considerations in low-temperature hybrid bonding processes. This paper first reviews the advancements in low-temperature Cu-based bonding technologies for advanced packaging. Various low-temperature Cu-Cu bonding techniques such as surface pretreatment, surface activation, structure modification, and orientation control have been proposed and investigated. To overcome coplanarity issues of Cu pillars and insufficient gaps for filling, low-temperature Cu-Cu bonding used, but it is still challenging in fine-pitch applications. Therefore, low-temperature Cu/SiO2, Cu/SiCN, and Cu/polymer hybrid bonding have been developed for advanced packaging applications. Furthermore, we present a novel hybrid bonding scheme for metal/polymer interfaces that achieves good flatness and an excellent bonding interface without the need for the chemical mechanical polishing (CMP) process.

A Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integration.

A novel method for the inspection of the stacking misalignment in three-dimensional integration circuit (3DIC) by using electrical measurement is proposed. The metal line pattern designed in this paper combined with bump-less TSV fabrication process can successfully detect the direction and quantity of stacking fault. In addition, circuit combined with testing structure can be developed and simulated by using the current mirror concept and offered measurements with better efficiency.

Asymmetric Low Temperature Bonding Structure with Thin Solder Layers Using Ultra-Thin Buffer Layer.

Asymmetric Cu to In/Sn bonding structure with Ni ultrathin buffer layer (UBL) on Cu side is investigated in this research. The usage of Ni UBL slows down intermetallic compound (IMC) formation during bonding. Asymmetric structure can separate electrical isolation and solder process to avoid interaction, which can prevent IMC formation during polymer curing. A well-bonded asymmetric structure can be achieved with submicron solder by 150 °C bonding for 15 min. The structure shows the potential for low temperature hybrid bonding technology in high-density three-dimensional (3D) integration.

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

Robust terahertz polarizers with high transmittance at selected frequencies through Si wafer bonding technologies.

Terahertz (THz) polarizers with robust structure and high transmittance are demonstrated using 3D-integrated circuit (IC) technologies. A Cu wire-grid polarizer is sealed and well protected by Si-bonded wafers through a low-temperature eutectic bonding method. Deep reactive-ion etching is used to fabricate the anti-reflection (AR) layers on outward surfaces of bonded wafers. The extinction ratio and transmittance of polarizers are between 20 dB and 33 dB, and 13 dB and 27 dB for 10 µm and 20 µm pitch wire-grids, respectively, and 100% at central frequency, depending on frequency and AR layer thickness. The process of polarizer fabrication is simple from mature semiconductor manufacturing techniques that lead to high yield, low cost, and potential for THz applications.

Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes.

Highly integrated neural sensing microsystems are crucial to capture accurate signals for brain function investigations. In this paper, a 256-channel neural sensing microsystem with a sensing area of 5 × 5 mm 2 is presented based on 2.5-D through-silicon-via (TSV) integration. This microsystem composes of dissolvable µ-needles, TSV-embedded µ-probes, 256-channel neural amplifiers, 11-bit area-power-efficient successive approximation register analog-to-digital converters, and serializers. This microsystem can detect 256 electrocorticography and local field potential signals within a small area of 5 mm × 5 mm. The neural amplifier realizes 57.8 dB gain with only 9.8 µW per channel. The overall power of this microsystem is only 3.79 mW for 256-channel neural sensing. A smaller microsystem with dimension of 6 mm × 4 mm has been also implanted into rat brain for somatosensory evoked potentials (SSEPs) recording by using contralateral and ipsilateral electrical stimuli with intensity from 0.2 to 1.0 mA, and successfully observed different SSEPs from left somatosensory cortex of a rat.

Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV).

3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper.

Sake Protein Supplementation Affects Exercise Performance and Biochemical Profiles in Power-Exercise-Trained Mice.

UNLABELLED: Exercise and fitness training programs have attracted the public's attention in recent years. Sports nutrition supplementation is an important issue in the global sports market. PURPOSE: In this study, we designed a power exercise training (PET) program with a mouse model based on a strength and conditional training protocol for humans. We tested the effect of supplementation with functional branched-chain amino acid (BCAA)-rich sake protein (SP) to determine whether the supplement had a synergistic effect during PET and enhanced athletic performance and resistance to fatigue. METHODS: Male ICR mice were divided into three groups (n = 8 per group) for four-week treatment: sedentary controls with vehicle (SC), and PET and PET groups with SP supplementation (3.8 g/kg, PET + SP). Exercise performance was evaluated by forelimb grip strength and exhaustive swimming time as well as changes in body composition and anti-fatigue activity levels of serum lactate, ammonia, glucose, and creatine kinase (CK) after a 15-min swimming exercise. The biochemical parameters were measured at the end of the experiment. RESULTS: four-week PET significantly increased grip strength and exhaustive swimming time and decreased epididymal fat pad (EFP) weight and area. Levels of aspartate aminotransferase (AST), alanine aminotransferase (ALT), creatinine, and uric acid (UA) were significantly increased. PET + SP supplementation significantly decreased serum lactate, ammonia and CK levels after the 15-min swimming exercise. The resting serum levels of AST, ALT, CREA and UA were all significantly decreased with PET + SP. CONCLUSION: The PET program could increase the exercise performance and modulate the body composition of mice. PET with SP conferred better anti-fatigue activity, improved biochemical profiles, and may be an effective ergogenic aid in strength training.

Low-temperature direct copper-to-copper bonding enabled by creep on (111) surfaces of nanotwinned Cu.

Direct Cu-to-Cu bonding was achieved at temperatures of 150-250 °C using a compressive stress of 100 psi (0.69 MPa) held for 10-60 min at 10(-3) torr. The key controlling parameter for direct bonding is rapid surface diffusion on (111) surface of Cu. Instead of using (111) oriented single crystal of Cu, oriented (111) texture of extremely high degree, exceeding 90%, was fabricated using the oriented nano-twin Cu. The bonded interface between two (111) surfaces forms a twist-type grain boundary. If the grain boundary has a low angle, it has a hexagonal network of screw dislocations. Such network image was obtained by plan-view transmission electron microscopy. A simple kinetic model of surface creep is presented; and the calculated and measured time of bonding is in reasonable agreement.

A double-sided, single-chip integration scheme using through-silicon-via for neural sensing applications.

We present a new double-sided, single-chip monolithic integration scheme to integrate the CMOS circuits and MEMS structures by using through-silicon-via (TSV). Neural sensing applications were chosen as the implementation example. The proposed heterogeneous device integrates standard 0.18 µm CMOS technology, TSV and neural probe array into a compact single chip device. The neural probe array on the back-side of the chip is connected to the CMOS circuits on the front-side of the chip by using low-parasitic TSVs through the chip. Successful fabrication results and detailed characterization demonstrate the feasibility and performance of the neural probe array, TSV and readout circuitry. The fabricated device is 5 × 5 mm(2) in area, with 16 channels of 150 µm-in-length neural probe array on the back-side, 200 µm-deep TSV through the chip and CMOS circuits on the front-side. Each channel consists of a 5 × 6 probe array, 3 × 14 TSV array and a differential-difference amplifier (DDA) based analog front-end circuitry with 1.8 V supply, 21.88 µW power consumption, 108 dB CMRR and 2.56 µVrms input referred noise. In-vivo long term implantation demonstrated the feasibility of presented integration scheme after 7 and 58 days of implantation. We expect the conceptual realization can be extended for higher density recording array by using the proposed method.

Quartz resonator assembling with TSV interposer using polymer sealing or metal bonding.

This paper presents one wafer level packaging approach of quartz resonator based on through-silicon via (TSV) interposer with metal or polymer bonding sealing of frequency components. The proposed silicon-based package of quartz resonator adopts several three-dimensional (3D) core technologies, such as Cu TSVs, sealing bonding, and wafer thinning. It is different from conventional quartz resonator using ceramic-based package. With evaluation of mechanical structure design and package performances, this quartz resonator with advanced silicon-based package shows great manufacturability and excellent performance to replace traditional metal lid with ceramic-based interposer fabrication approach.

Conductivity enhancement of multiwalled carbon nanotube thin film via thermal compression method.

For the first time, the thermal compression method is applied to effectively enhance the electrical conductivity of carbon nanotube thin films (CNTFs). With the assistance of heat and pressure on the CNTFs, the neighbor multiwalled carbon nanotubes (CNTs) start to link with each other, and then these separated CNTs are twined into a continuous film while the compression force, duration, and temperature are quite enough for the reaction. Under the compression temperature of 400°C and the compression force of 100 N for 50 min, the sheet resistance can be reduced from 17 to 0.9 k Ω/sq for the CNTFs with a thickness of 230 nm. Moreover, the effects of compression temperature and the duration of thermal compression on the conductivity of CNTF are also discussed in this work.

2.5D heterogeneously integrated microsystem for high-density neural sensing applications.

Heterogeneously integrated and miniaturized neural sensing microsystems are crucial for brain function investigation. In this paper, a 2.5D heterogeneously integrated bio-sensing microsystem with µ-probes and embedded through-silicon-via (TSVs) is presented for high-density neural sensing applications. This microsystem is composed of µ-probes with embedded TSVs, 4 dies and a silicon interposer. For capturing 16-channel neural signals, a 24 × 24 µ-probe array with embedded TSVs is fabricated on a 5×5 mm(2) chip and bonded on the back side of the interposer. Thus, each channel contains 6 × 6 µ -probes with embedded TSVs. Additionally, the 4 dies are bonded on the front side of the interposer and designed for biopotential acquisition, feature extraction and classification via low-power analog front-end (AFE) circuits, area-power-efficient analog-to-digital converters (ADCs), configurable discrete wavelet transforms (DWTs), filters, and a MCU. An on-interposer bus ( µ-SPI) is designed for transferring data on the interposer. Finally, the successful in-vivo test demonstrated the proposed 2.5D heterogeneously integrated bio-sensing microsystem. The overall power of this microsystem is only 676.3 µW for 16-channel neural sensing.

Adhesive selection and bonding parameter optimization for hybrid bonding in 3D integration.

Hybrid bonding, an emerging bonding approach with high yield and reliability, can achieve vertical interconnection with adhesive serving reinforcement of the mechanical stability between stacked ICs. To develop metal/adhesive hybrid bonding technology, four kinds of polymer materials, BCB, SU-8, AL-Polymer, and PI, were evaluated as the bonding adhesive. The compatibility between each polymer and metal was investigated, and the application range of each material was established thereof. Furthermore, the scheme of Cu-Sn-Cu interconnection hybridized with patterned BCB was designed and evaluated. Two key factors were discussed and optimized to perform the bonding integrity. The evaluation results and successful metal/adhesive hybrid bonding demonstration are disclosed in the paper.

Effects of bonding technology and thinning process in three-dimensional integration on device characteristics.

This research is to investigate the effects of bonding technology and thinning process on the electrical properties of 0.35 microm technology node n-MOSFET devices. After the bonding process, by changing the bonding temperature up to 400 degrees C and bonding force up to 2.5 x 10(5) Pa, these devices still have the same electrical performances. In addition, thinning process was applied to investigate the stress which would affect the electrical properties of n-MOSFETs. The electrical performances of devices do not change for substrate thickness larger than 466 microm.

The fabrication of a programmable via using phase-change material in CMOS-compatible technology.

We demonstrate an energy-efficient programmable via concept using indirectly heated phase-change material. This via structure has maximum phase-change volume to achieve a minimum on resistance for high performance logic applications. Process development and material investigations for this device structure are reported. The device concept is successfully demonstrated in a standard CMOS-compatible technology capable of multiple cycles between on/off states for reconfigurable applications.