ABSTRACT
Crack formation is typically undesirable as it represents mechanical failure that compromises strength and integrity. Recently, there have also been numerous attempts to control crack formation in materials with the aim to prevent or isolate crack propagation. In this work, we utilize fragmentation, at submicron and nanometre scales, to create ordered metal oxide film coatings. We introduce a simple method to create modified films using electroplating on a prepatterned substrate. The modified films undergo preferential fragmentation at locations defined by the initial structures on the substrate, yielding ordered structures. In thicker films, some randomness in the characteristic sizes of the fragments is introduced due to competition between crack propagation and crack creation. The method presented allows patterning of metal oxide films over relatively large areas by controlling the fragmentation process. We demonstrate use of the method to fabricate high-performance electrochromic structures, yielding good coloration contrast and high coloration efficiency.
ABSTRACT
Electrical and interfacial properties of metal-oxide-semiconductor (MOS) capacitors fabricated using atomic layer deposited bilayer TiO2/Al2O3 films on In0.53Ga0.47As/InP substrates are reported. Vacuum annealing at 350 °C is shown to improve the interface quality. Capacitance-voltage (C-V) characteristics with higher accumulation capacitance, negligible frequency dispersion, small hysteresis and low interface state density (â¼1.5 × 10(11) cm(-2) eV(-1)) have been observed for MOS capacitors. Low frequency (1/f) noise characterization and inelastic electron tunneling spectroscopy (IETS) studies have been performed to determine defects and interface traps and explain the lattice dynamics and trap state generation mechanisms. Both the IETS and 1/f noise studies reveal the spatial locations of the traps near the interface and also the nature of the traps. The IETS study further revealed the dynamic evolution of trap states related to low frequency noise sources in the deposited TiO2/Al2O3 stacks. It is shown that deposition of an ultrathin layer of TiO2 on Al2O3 can effectively control the diffusion of As in the dielectric and the oxidation states of In and Ga at the In0.53Ga0.47As surface.
ABSTRACT
High quality surface passivation on bulk-GaAs substrates and epitaxial-GaAs/Ge (epi-GaAs) layers were achieved by using atomic layer deposited (ALD) titanium aluminum oxide (TiAlO) alloy dielectric. The TiAlO alloy dielectric suppresses the formation of defective native oxide on GaAs layers. X-ray photoelectron spectroscopy (XPS) analysis shows interfacial arsenic oxide (As(x)O(y)) and elemental arsenic (As) were completely removed from the GaAs surface. Energy dispersive X-ray diffraction (EDX) analysis and secondary ion mass spectroscopy (SIMS) analysis showed that TiAlO dielectric is an effective barrier layer for reducing the out-diffusion of elemental atoms, enhancing the electrical properties of bulk-GaAs based metal-oxide-semiconductor (MOS) devices. Moreover, ALD TiAlO alloy dielectric on epi-GaAs with AlGaAs buffer layer realized smooth interface between epi-GaAs layers and TiAlO dielectric, yielding a high quality surface passivation on epi-GaAs layers, much sought-after for high-speed transistor applications on a silicon platform. Presence of a thin AlGaAs buffer layer between epi-GaAs and Ge substrates improved interface quality and gate dielectric quality through the reduction of interfacial layer formation (Ga(x)O(y)) and suppression of elemental out-diffusion (Ga and As). The AlGaAs buffer layer and TiAlO dielectric play a key role to suppress the roughening, interfacial layer formation, and impurity diffusion into the dielectric, which in turn largely enhances the electrical property of the epi-GaAs MOS devices.
ABSTRACT
In this work, we show how the vacancy diffusion length scale must be considered, in the context of the diameter of a nanowire, when utilizing the Kirkendall phenomenon in the fabrication of metal oxide nanotubes starting from metal nanowires. We find that the diameter of the nanowire relative to the diffusion length scale of the vacancy will affect greatly the type of voids that can be generated. By using a larger diameter nickel nanowire, we show that segmented heterojunction void formation can be avoided and that the resulting structure will serve as a precursory 'template' for subsequent oxidation processes at high temperatures. In doing so, we can prevent the formation of bamboo-like structures and obtain uniform nickel oxide nanotubes through direct oxidation that has proven to be difficult previously. The result from this work is also significant as the interplay of vacancy diffusion length and nanostructure dimension is important in the oxidation of other types of metal nanostructures, especially when void formation and the Kirkendall effect are involved.
ABSTRACT
We report on a method to fabricate one-dimensional heterostructures of germanium nanowires (GeNWs) and germanium-silicon oxide nanotubes (GeSiO(x)NTs). The synthesis of the wire-tube heterostructures is carried out using a simple furnace set-up with germanium tetraiodide and germanium powders as growth precursors, gold-dotted silicon wafers as substrates and by controlling the temperature ramp rate/sequence of the growth precursors. Two types of wire-tube heterostructures resulting from distinct growth mechanisms are obtained. The type-1 heterostructure consists of a GeNW, grown via a gold-catalyzed vapour-liquid-solid process, at the lower end and a GeSiO(x)NT at the upper end. In contrast, the type-2 heterostructure is made up of a solid wire at the upper end and a hollow tube at the lower end. The solid wire portion of the type-2 heterostructure is formed through an oxide-assisted growth process.
