Remarkably fast and reusable photocatalysis by UV annealed Cu2O-SnO2 p-n heterojunction.

Powdered micro- or nano-particles photocatalyst has separation and recovery challenges, which may create a second pollution to environment and harmful to animals. To address those issues, SnO2, Cu2O and Cu2O-SnO2 p-n heterojunction thin films are formed on glass substrates using efficient co-sputtering method that is commonly employed for large-area high-definition display panel. Using first-order kinetics, 100 °C ultraviolet (UV) annealed Cu2O-SnO2 p-n heterojunction shows the superb fast degradation rate constant of 0.21 and 0.16 min-1 for methylene blue (MB) and methyl orange (MO) organic dyes, respectively, as photogenerated electron-hole pairs is increased. Record best degradation rate constants of 0.19 and 0.11 min-1 for respective MB and MO are still achieved even after four repeated cycles. The 100 °C UV annealed Cu2O-SnO2 film catalyst displays greater degradation efficiency in both dyes, reaching 100% degradation at room temperature after 30 and 35 min of illumination for MB and MO respectively. The scavenger experiments show that hydroxyl (·OH) and superoxide radicals (·O2-) are the major active species in the degradation of dye. The 100 °C UV annealed Cu2O-SnO2 film catalyst showed stability as well as reusability towards the dye degradation. As a result, the present work delivers an effective way to enhance the photocatalytic performance and also an easy recovery of the catalyst, which can be explored for various emerging pollutants.

Superior High Transistor's Effective Mobility of 325 cm2/V-s by 5 nm Quasi-Two-Dimensional SnON nFET.

This work reports the first nanocrystalline SnON (7.6% nitrogen content) nanosheet n-type Field-Effect Transistor (nFET) with the transistor's effective mobility (µeff) as high as 357 and 325 cm2/V-s at electron density (Qe) of 5 × 1012 cm-2 and an ultra-thin body thickness (Tbody) of 7 nm and 5 nm, respectively. At the same Tbody and Qe, these µeff values are significantly higher than those of single-crystalline Si, InGaAs, thin-body Si-on-Insulator (SOI), two-dimensional (2D) MoS2 and WS2. The new discovery of a slower µeff decay rate at high Qe than that of the SiO2/bulk-Si universal curve was found, owing to a one order of magnitude lower effective field (Eeff) by more than 10 times higher dielectric constant (κ) in the channel material, which keeps the electron wave-function away from the gate-oxide/semiconductor interface and lowers the gate-oxide surface scattering. In addition, the high µeff is also due to the overlapped large radius s-orbitals, low 0.29 mo effective mass (me*) and low polar optical phonon scattering. SnON nFETs with record-breaking µeff and quasi-2D thickness enable a potential monolithic three-dimensional (3D) integrated circuit (IC) and embedded memory for 3D biological brain-mimicking structures.

Remarkably High-Performance Nanosheet GeSn Thin-Film Transistor.

High-performance p-type thin-film transistors (pTFTs) are crucial for realizing low-power display-on-panel and monolithic three-dimensional integrated circuits. Unfortunately, it is difficult to achieve a high hole mobility of greater than 10 cm2/V·s, even for SnO TFTs with a unique single-hole band and a small hole effective mass. In this paper, we demonstrate a high-performance GeSn pTFT with a high field-effect hole mobility (µFE), of 41.8 cm2/V·s; a sharp turn-on subthreshold slope (SS), of 311 mV/dec, for low-voltage operation; and a large on-current/off-current (ION/IOFF) value, of 8.9 × 106. This remarkably high ION/IOFF is achieved using an ultra-thin nanosheet GeSn, with a thickness of only 7 nm. Although an even higher hole mobility (103.8 cm2/V·s) was obtained with a thicker GeSn channel, the IOFF increased rapidly and the poor ION/IOFF (75) was unsuitable for transistor applications. The high mobility is due to the small hole effective mass of GeSn, which is supported by first-principles electronic structure calculations.

Improved Device Distribution in High-Performance SiNx Resistive Random Access Memory via Arsenic Ion Implantation.

Large device variation is a fundamental challenge for resistive random access memory (RRAM) array circuit. Improved device-to-device distributions of set and reset voltages in a SiNx RRAM device is realized via arsenic ion (As+) implantation. Besides, the As+-implanted SiNx RRAM device exhibits much tighter cycle-to-cycle distribution than the nonimplanted device. The As+-implanted SiNx device further exhibits excellent performance, which shows high stability and a large 1.73 × 103 resistance window at 85 °C retention for 104 s, and a large 103 resistance window after 105 cycles of the pulsed endurance test. The current-voltage characteristics of high- and low-resistance states were both analyzed as space-charge-limited conduction mechanism. From the simulated defect distribution in the SiNx layer, a microscopic model was established, and the formation and rupture of defect-conductive paths were proposed for the resistance switching behavior. Therefore, the reason for such high device performance can be attributed to the sufficient defects created by As+ implantation that leads to low forming and operation power.

Effects of Microwave and Furnace Annealing for P-Type SnO Thin Film Material in Oxygen Ambient.

Transparent conductive oxide (TCO) semiconductors are attracted considerable attention due to a wide range of applications, such as flat panel display (FPD), touch panels, solar cells, and other optoelectronic devices. Owing to the different carrier conduction paths between n-type and P-type TCOs, the n-type TCO used in TFTs usually have high Ion/Ioff current ratio (>107) and high electron mobility (>10 cm²/V·s), P-type TCO TFTs are both lower than that of n-type one. For complementary circuits design and applications, however, both P-type and n-type semiconductor materials are equally important. For SnO thin films, it is important to adjust the ratio of Sn2+ (SnO P-type) and Sn4+ (SnO2 n-type) in order to modulate the electrical characteristics. In this investigation of post treatment for SnO thin films, both microwave annealing (MWA) and furnace annealing process with 02 ambient are studied. The results show that SnO thin films are optimized at 300 °C, 30 minutes furnace annealing, the P-type SnO/SnO2 thin film shows surface mean roughness 0.168 nm, [Sn2+]/[Sn4+] ratio as 0.838, at least 80% transmittance between 380 nm-700 nm visible light. Withthe results, SnO can be even used to fabricate high performance P-type thin film transistors (TFTs) device for future applications.

Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer.

Implementing high-performance n- and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. To achieve these goals, a top-gate transistor is preferred to a conventional bottom-gate structure. However, achieving high-performance top-gate p-TFT with good hole field-effect mobility (µFE) and large on-current/off-current (ION/IOFF) is challenging. In this report, coplanar top-gate nanosheet SnO p-TFT with high µFE of 4.4 cm2/Vs, large ION/IOFF of 1.2 × 105, and sharp transistor's turn-on subthreshold slopes (SS) of 526 mV/decade were achieved simultaneously. Secondary ion mass spectrometry analysis revealed that the excellent device integrity was strongly related to process temperature, because the HfO2/SnO interface and related µFE were degraded by Sn and Hf inter-diffusion at an elevated temperature due to weak Sn-O bond enthalpy. Oxygen content during process is also crucial because the hole-conductive p-type SnO channel is oxidized into oxygen-rich n-type SnO2 to demote the device performance. The hole µFE, ION/IOFF, and SS values obtained in this study are the best-reported data to date for top-gate p-TFT device, thus facilitating the development of monolithic 3D ICs on the backend dielectric of IC chips.

Charge transport mechanism in the forming-free memristor based on silicon nitride.

Nonstoichiometric silicon nitride SiNx is a promising material for developing a new generation of high-speed, reliable flash memory device based on the resistive effect. The advantage of silicon nitride over other dielectrics is its compatibility with the silicon technology. In the present work, a silicon nitride-based memristor deposited by the plasma-enhanced chemical vapor deposition method was studied. To develop a memristor based on silicon nitride, it is necessary to understand the charge transport mechanisms in all states. In the present work, it was established that the charge transport in high-resistance states is not described by the Frenkel effect model of Coulomb isolated trap ionization, Hill-Adachi model of overlapping Coulomb potentials, Makram-Ebeid and Lannoo model of multiphonon isolated trap ionization, Nasyrov-Gritsenko model of phonon-assisted tunneling between traps, Shklovskii-Efros percolation model, Schottky model and the thermally assisted tunneling mechanisms. It is established that, in the initial state, low-resistance state, intermediate-resistance state and high-resistance state, the charge transport in the forming-free SiNx-based memristor is described by the space charge limited current model. The trap parameters responsible for the charge transport in various memristor states are determined.

Electronic structure and charge transport mechanism in a forming-free SiO x -based memristor.

THe memristor is a key memory element for neuromorphic electronics and new generation flash memories. One of the most promising materials for memristor technology is silicon oxide SiO x , which is compatible with silicon-based technology. In this paper, the electronic structure and charge transport mechanism in a forming-free SiO x -based memristor fabricated with the plasma enhanced chemical vapor deposition method is investigated. The experimental current-voltage characteristics measured at different temperatures in high-resistance, low-resistance and intermediate states are compared with various charge transport theories. The charge transport in all states is limited by the space charge-limited current model. The trap parameters, responsible for the charge transport in a SiO x -based memristor in different states, are determined.

High-Performance Top-Gate Thin-Film Transistor with an Ultra-Thin Channel Layer.

Metal-oxide thin-film transistors (TFTs) have been implanted for a display panel, but further mobility improvement is required for future applications. In this study, excellent performance was observed for top-gate coplanar binary SnO2 TFTs, with a high field-effect mobility (µFE) of 136 cm2/Vs, a large on-current/off-current (ION/IOFF) of 1.5 × 108, and steep subthreshold slopes of 108 mV/dec. Here, µFE represents the maximum among the top-gate TFTs made on an amorphous SiO2 substrate, with a maximum process temperature of ≤ 400 °C. In contrast to a bottom-gate device, a top-gate device is the standard structure for monolithic integrated circuits (ICs). Such a superb device integrity was achieved by using an ultra-thin SnO2 channel layer of 4.5 nm and an HfO2 gate dielectric with a 3 nm SiO2 interfacial layer between the SnO2 and HfO2. The inserted SiO2 layer is crucial for decreasing the charged defect scattering in the HfO2 and HfO2/SnO2 interfaces to increase the mobility. Such high µFE, large ION, and low IOFF top-gate SnO2 devices with a coplanar structure are important for display, dynamic random-access memory, and monolithic three-dimensional ICs.

High Performance All Nonmetal SiNx Resistive Random Access Memory with Strong Process Dependence.

All-nonmetal resistive random access memory (RRAM) with a N+-Si/SiNx/P+-Si structure was investigated in this study. The device performance of SiNx developed using physical vapor deposition (PVD) was significantly better than that of a device fabricated using plasma-enhanced chemical vapor deposition (PECVD). The SiNx RRAM device developed using PVD has a large resistance window that is larger than 104 and exhibits good endurance to 105 cycles under switching pulses of 1 µs and a retention time of 104 s at 85 °C. Moreover, the SiNx RRAM device developed using PVD had tighter device-to-device distribution of set and reset voltages than those developed using PECVD. Such tight distribution is crucial to realise a large-size cross-point array and integrate with complementary metal-oxide-semiconductor technology to realise electronic neurons. The high performance of the SiNx RRAM device developed using PVD is attributed to the abundant defects in the PVD dielectric that was supported by the analysed conduction mechanisms obtained from the measured current-voltage characteristics.

Reliability of Atmosphere Pressure-Plasma Enhanced Chemical Vapor Deposition Deposited Indium Gallium Zinc Oxide Resistive Random Access Memory Device with Microwave Annealing.

Recently resistive random access memory (RRAM) is considered to be the most promising one to become the next generation memory since its simple Metal/Insulator/Metal (MIM) structure, lower power consumption and fabrication cost (Meena, J.S., et al., 2014. Overview of emerging nonvolatile memory technologies. Nanoscale Research Letters, 9(1), p.526). Due to some bottlenecks for current flash memory, such as high operation voltage, low operation speed, poor retention time and endurance, RRAM device is regarded as an alternative solution (Fuh, C.S., et al., 2011. Role of environmental and annealing conditions on the passivation-free In-Ga-Zn-O TFT. Thin Solid Films, 520, pp.1489-1494). In this investigation, the memory layer of RRAM device is IGZO, and it is deposited with AP-PECVD technique which can operate under atmosphere, reduce cost of the process. Microwave annealing (MWA) is used to enhance the RRAM device reliability (Fuh, C.S., et al., 2011. Role of environmental and annealing conditions on the passivation-free In-Ga-Zn-O TFT. Thin Solid Films, 520, pp.1489-1494). Experiment shows that with appropriate MWA treatment, the IGZO RRAM device exhibits better electrical characteristics, reliability issues such as numbers of switching cycle and data retention time are also improved (Teng, L.F., et al., 2012. Effects of microwave annealing on electrical enhancement of amorphous oxide semiconductor thin film transistor. Applied Physics Letters, 101, p.132901).

Study of Atmospheric-Pressure Plasma Enhanced Chemical Vapor Deposition Fabricated Indium Gallium Zinc Oxide Thin Film Transistors with In-Situ Hydrogen Plasma Treatment.

Amorphous InGaZnO (a-IGZO) Thin Film Transistors (TFTs) has been studied extensively for their perspective applications in next generation active-matrix displays such as liquid crystal displays and flat-panel displays, due to its better field-effect mobility (>10 cm²/V · S), larger Ion/Ioff ratio (>106), and better stability electrical. Hydrogen is known as shallow donors for n-type (channel) oxide semiconductors (Dong, J.J., et al. 2010. Effects of hydrogen plasma treatment on the electrical and optical properties of Zno films: Identification of hydrogen donors in ZnO. ACS Appl. Mater. Interfaces, 2, pp.1780-1784), and it is also effective passivator for traps (Tsao, S.W., et al., 2010. Hydrogen-induced improvements in electrical characteristics of a-IGZO thin-film transistors. Solid-State Electron, 54, pp.1497-1499). In this study, In-Situ hydrogen plasma is applied to deposit IGZO channel. With atmospheric-pressure PECVD (AP-PECVD), IGZO thin film can be deposited without vacuum system, large area manufacturing, and cost reducing (Chang, K.M., et al., 2011. Transparent conductive indium-doped zinc oxide films prepared by atmospheric pressure plasma jet. Thin Solid Films, 519, pp.5114-5117). The results show that with appropriate flow ratio of Ar/H2 plasma treatment, the a-IGZO TFT device exhibits better performance with mobility (µFE) 19.7 cm²/V · S, threshold voltage (VT) 1.18 V, subthreshold swing (SS) 81 mV/decade, and Ion/Ioff ratio 5.35×107.

Investigation of Microwave Annealing on Resistive Random Access Memory Device with Atmospheric Pressure Plasma Enhanced Chemical Vapor Deposition Deposited IGZO Layer.

Non-volatile memory (NVM) is essential in almost every consumer electronic products. The most prevalent NVM used nowadays is flash memory (Meena, J.S., et al., 2014. Overview of emerging nonvolatile memory technologies. Nanoscale Res. Letters, 9(1), p.526). However, some bottlenecks of flash memory have been identified, such as high operation voltage, low operation speed, and poor retention time. Resistive random access memory (RRAM) is considered to be the most promising one to become the next generation NVM device since its simple structure, fast program/erase speed, and low power consumption. In this experiment, the RRAM device is fabricated, and its IGZO (memory) layer is deposited with AP-PECVD technique which can reduce cost of the process. Microwave annealing (MWA) is used to enhance electrical characteristics of the RRAM device (Fuh, C.S., et al., 2011. Role of environmental and annealing conditions on the passivation-free In-Ga- Zn-O TFT. Thin Solid Films, 520, pp.1489-1494). Experiment results show that with appropriate MWA treatment, the IGZO RRAM device exhibits better electrical characteristics under bipolar operation, all forming/set/reset voltage for RRAM device is simultaneously lowered.

Novel Technique for Full-Thickness Abdominal Wall Closure in Laparoscopic Ventral Hernia Repair.

Laparoscopic ventral hernia repair incorporating a prosthetic mesh underlay, first described in 1993, has demonstrated a lower long-term recurrence rate versus open non-mesh repair. However, over the past 25 years, the laparoscopic approach to ventral/incisional hernias is utilized in only approximately 30% of cases. One of the reasons that prevents it from being utilized more often is the inability to readily, reliably, and easily close the fascial defect. A novel technique has been developed for full-thickness abdominal wall closure in laparoscopic ventral hernioplasty, utilizing puncture sites to place multiple self-locking ligature straps. Introduction of the straps into the abdominal cavity in orthogonal orientation to the skin surface, followed by subcutaneous retrieval of the contralateral tip of the strap, achieves incorporation of full-thickness abdominal wall on either side of the defect. The self-locking property of each strap allows tension to be applied in sequential fashion. Incremental tension application facilitates re-apposition of the borders in large defects. The increased width of the strap compared with conventional suture serves to resolve the force exerted upon tissue during the acute phase of defect closure. The instrumentation was tested in six ventral hernias created in resected porcine belly walls. Subsequent tests were conducted in three swine with large congenital umbilical hernias. One of the test animals was re-examined laparoscopically 30 days post repair, with full healing and no recurrence exhibited upon re-examination. We anticipate that the simplicity and functionality of this technique will translate to clinical utility in the significant cohort of human ventral hernia patients.

Forming-Free SiGeOx/TiOy Resistive Random Access Memories Featuring Large Current Distribution Windows.

Optimal device integrity was achieved in Ni/SiGeOx/TiOy/TaN resistive memory by using a forming-free switch with a low switching power of 790 µW, stable endurance of 104 cycles, optimal retention time of 105 s, resistance window of at least 1150×, and tight current distributions at 85 °C. These characteristics are attributed to the low current switching obtained using SiGeOx with a high oxygen vacancy density and highly defective TiOy grain boundaries.

All Nonmetal Resistive Random Access Memory.

Traditional Resistive Random Access Memory (RRAM) is a metal-insulator-metal (MIM) structure, in which metal oxide is usually used as an insulator. The charge transport mechanism of traditional RRAM is attributed to a metallic filament inside the RRAM. In this paper, we demonstrated a novel RRAM device with no metal inside. The N+-Si/SiOx/P+-Si combination forms a N+IP+ diode structure that is different from traditional MIM RRAM. A large high-resistance/low-resistance window of 1.9 × 104 was measured at room temperature. A favorable retention memory window of 1.2 × 103 was attained for 104 s at 85 °C. The charge transport mechanism of virgin, high- and low-resistance states can be well modeled by the single Shklovskii-Efros percolation mechanism rather than the charge transport in metallic filament. X-ray photoelectron spectroscopy demonstrated that the value of x in SiOx was 0.62, which provided sufficient oxygen vacancies for set/reset RRAM functions.

Remarkably High Hole Mobility Metal-Oxide Thin-Film Transistors.

High performance p-type thin-film transistor (p-TFT) was realized by a simple process of reactive sputtering from a tin (Sn) target under oxygen ambient, where remarkably high field-effect mobility (µ FE ) of 7.6 cm2/Vs, 140 mV/dec subthreshold slope, and 3 × 104 on-current/off-current were measured. In sharp contrast, the SnO formed by direct sputtering from a SnO target showed much degraded µ FE , because of the limited low process temperature of SnO and sputtering damage. From the first principle quantum-mechanical calculation, the high hole µ FE of SnO p-TFT is due to its considerably unique merit of the small effective mass and single hole band without the heavy hole band. The high performance p-TFTs are the enabling technology for future ultra-low-power complementary-logic circuits on display and three-dimensional brain-mimicking integrated circuits.

Remarkably High Mobility Thin-Film Transistor on Flexible Substrate by Novel Passivation Material.

High mobility thin-film transistor (TFT) is crucial for future high resolution and fast response flexible display. Remarkably high performance TFT, made at room temperature on flexible substrate, is achieved with record high field-effect mobility (µ FE ) of 345 cm2/Vs, small sub-threshold slope (SS) of 103 mV/dec, high on-current/off-current (I ON /I OFF ) of 7 × 106, and a low drain-voltage (VD) of 2 V for low power operation. The achieved mobility is the best reported data among flexible electronic devices, which is reached by novel HfLaO passivation material on nano-crystalline zinc-oxide (ZnO) TFT to improve both I ON and I OFF . From X-ray photoelectron spectroscopy (XPS) analysis, the non-passivated device has high OH-bonding intensity in nano-crystalline ZnO, which damage the crystallinity, create charged scattering centers, and form potential barriers to degrade mobility.

A Novel Read Scheme for Large Size One-Resistor Resistive Random Access Memory Array.

The major issue of RRAM is the uneven sneak path that limits the array size. For the first time record large One-Resistor (1R) RRAM array of 128x128 is realized, and the array cells at the worst case still have good Low-/High-Resistive State (LRS/HRS) current difference of 378 nA/16 nA, even without using the selector device. This array has extremely low read current of 9.7 µA due to both low-current RRAM device and circuit interaction, where a novel and simple scheme of a reference point by half selected cell and a differential amplifier (DA) were implemented in the circuit design.

New Material Transistor with Record-High Field-Effect Mobility among Wide-Band-Gap Semiconductors.

At an ultrathin 5 nm, we report a new high-mobility tin oxide (SnO2) metal-oxide-semiconductor field-effect transistor (MOSFET) exhibiting extremely high field-effect mobility values of 279 and 255 cm(2)/V-s at 145 and 205 °C, respectively. These values are the highest reported mobility values among all wide-band-gap semiconductors of GaN, SiC, and metal-oxide MOSFETs, and they also exceed those of silicon devices at the aforementioned elevated temperatures. For the first time among existing semiconductor transistors, a new device physical phenomenon of a higher mobility value was measured at 45-205 °C than at 25 °C, which is due to the lower optical phonon scattering by the large SnO2 phonon energy. Moreover, the high on-current/off-current of 4 × 10(6) and the positive threshold voltage of 0.14 V at 25 °C are significantly better than those of a graphene transistor. This wide-band-gap SnO2 MOSFET exhibits high mobility in a 25-205 °C temperature range, a wide operating voltage of 1.5-20 V, and the ability to form on an amorphous substrate, rendering it an ideal candidate for multifunctional low-power integrated circuit (IC), display, and brain-mimicking three-dimensional IC applications.