Low-Power Wireless Sensor Network Using Fine-Grain Control of Sensor Module Power Mode.

Wireless sensor nodes are heavily resource-constrained due to their edge form factor, which has motivated increasing battery life through low-power techniques. This paper proposes a power management method that leads to less energy consumption in an idle state than conventional power management systems used in wireless sensor nodes. We analyze and benchmark the power consumption between Sleep, Idle, and Run modes. To reduce sensor node power consumption, we develop fine-grained power modes (FGPM) with five states which modulate energy consumption according to the sensor node's communication status. We evaluate the proposed method on a test bench Mica2. As a result, the power consumed is 74.2% lower than that of conventional approaches. The proposed method targets the reduction of power consumption in IoT sensor modules with long sleep mode or short packet data in which most networks operate.

Nano-Crossbar Weighted Memristor-Based Convolution Neural Network Architecture for High-Performance Artificial Intelligence Applications.

Nano memristor crossbar arrays, which can represent analog signals with smaller silicon areas, are popularly used to describe the node weights of the neural networks. The crossbar arrays provide high computational efficiency, as they can perform additions and multiplications at the same time at a cross-point. In this study, we propose a new approach for the memristor crossbar array architecture consisting of multi-weight nano memristors on each cross-point. As the proposed architecture can represent multiple integer-valued weights, it can enhance the precision of the weight coefficients in comparison with the existing memristor-based neural networks. This study presents a Radix-11 nano memristor crossbar array with weighted memristors; it validates the operations of the circuits, which use the arrays through circuit-level simulation. With the proposed Radix-11 approach, it is possible to represent eleven integer-valued weights. In addition, this study presents a neural network designed using the proposed Radix-11 weights, as an example of high-performance AI applications. The neural network implements a speech-keyword detection algorithm, and it was designed on a TensorFlow platform. The implemented keyword detection algorithm can recognize 35 Korean words with an inferencing accuracy of 95.45%, reducing the inferencing accuracy only by 2% when compared to the 97.53% accuracy of the real-valued weight case.

Quantized Convolutional Neural Network Implementation on a Parallel-Connected Memristor Crossbar Array for Edge AI Platforms.

There are many challenges in the hardware implementation of a neural network using nanoscale memristor crossbar arrays where the use of analog cells is concerned. Multi-state or analog cells introduce more stringent noise margins, which are difficult to adhere to in light of variability. We propose a potential solution using a 1-bit memristor that stores binary values "0" or "1" with their memristive states, denoted as a high-resistance state (HRS) and a low-resistance state (LRS). In addition, we propose a new architecture consisting of 4-parallel 1-bit memristors at each crosspoint on the array. The four 1-bit memristors connected in parallel represent 5 decimal values according to the number of activated memristors. This is then mapped to a synaptic weight, which corresponds to the state of an artificial neuron in a neural network. We implement a convolutional neural network (CNN) model on a framework (tensorflow) using an equivalent quantized weight mapping model that demonstrates learning results almost identical to a high-precision CNN model. This radix-5 CNN is mapped to hardware on the proposed parallel-connected memristor crossbar array. Also, we propose a method for negative weight representation on a memristor crossbar array. Then, we verify the CNN hardware on an edge-AI (e-AI) platform, developed on a field-programmable gate array (FPGA). In this e-AI platform, we represent five weights per crosspoint using CLB logics. We test the learning results of the CNN hardware using an e-AI platform with a dataset consisting of 4×4 images in three classes. We verify the functionality of our radix-5 CNN implementation showing comparable classification accuracy to high-precision use cases, with reduction of the area of the memristor crossbar array by half, all verified on a FPGA. Implementing the CNN model on the FPGA board can contribute to the practical use of edge-AI.

A Leaky-Integrate-and-Fire Neuron Model of Spontaneous Reset of Thin-Film Metal-Oxide Resistive Switches.

Resistive switches in crossbar arrays introduce one potential option to push past the limits of CMOS process scaling, with advantages including low switching thresholds (<3 V), high integrability with CMOS, and fast switching speeds (<10 ns). These typically employ a 1T1R scheme for each cell, where the transistor is deployed for selection and sneak path mitigation. However, when conductive filaments are formed in metal-oxide resistive switches, it is often the case that analog states are not thermodynamically favorable, and will spontaneously set or reset to a more stable state. This causes stochastic switching, variability, and non-reproducibility, in a manner which cannot be harnessed in stochastic gradient descent. Equally important is the memory leakage problem that is introduced. In this work, we present a generalized neuron model of resistive switching in the development of a phase plane characterization, and verify its operation by comparing it to our own in-house fabricated thin-film titanium-oxide memristor array. We show an alternative design methodology that draws inspiration from the leaky-integrate-and-fire neuron model. The advantages exhibited by such a methodology are to provide more biologically accurate neuronal model and to enable large scale simulations, demonstrated by the 30% improvement in speed over similar device models.

Nano-Programmable Logics Based on Double-Layer Anti-Facing Memristors.

The memristor, as theorized by Chua in 1971 (L. Chua, IEEE Trans. Circuit Theory 18, 507 (1971)), is a two-terminal device whose resistance state is based on the history of charge flow brought about as a result of the voltage applied across its terminals. High-density regular fabrics for nanoscale memristors, such as crossbar arrays, are emerging architectures for system-on-chip (SoC) implementation, which provide both simplified structure and improved performance (W. H. Yu, et al., IEEE Trans. VLSI 20, 1012 (2012)). The advantage of using memristors as the switching devices within crossbar arrays is their nanoscale switching capability, which specifically changes their resistance state between high and low. In this paper, we propose a new nano-programmable logic array (PLA) device in the form of an on anti-facing double-layer memristor array. The PLA is composed of an AND plane and an OR plane merged onto the same layer. The AND and OR planes are stacked vertically such that each layer forms a crossbar architecture; thus, a cross section reveals two anti-facing memristors with 5 layers: the bottom metal layer, a memristive layer, the intermediate metal layer, an anti-facing memristive layer, and the top metal layer. The intermediate metal layer provides its output at the AND plane which is the input of the OR plane, and as such, the input and output nodes of the two logic functions are shared. Thus, the proposed architecture reduces the propagation delay of the AND plane by 70% by sharing the OR plane input wires. Additionally, the anti-facing architecture makes it easy to determine appropriate values for the pull-up and pull-down registers of the PLA.

Formulation and Implementation of Nonlinear Integral Equations to Model Neural Dynamics Within the Vertebrate Retina.

Existing computational models of the retina often compromise between the biophysical accuracy and a hardware-adaptable methodology of implementation. When compared to the current modes of vision restoration, algorithmic models often contain a greater correlation between stimuli and the affected neural network, but lack physical hardware practicality. Thus, if the present processing methods are adapted to complement very-large-scale circuit design techniques, it is anticipated that it will engender a more feasible approach to the physical construction of the artificial retina. The computational model presented in this research serves to provide a fast and accurate predictive model of the retina, a deeper understanding of neural responses to visual stimulation, and an architecture that can realistically be transformed into a hardware device. Traditionally, implicit (or semi-implicit) ordinary differential equations (OES) have been used for optimal speed and accuracy. We present a novel approach that requires the effective integration of different dynamical time scales within a unified framework of neural responses, where the rod, cone, amacrine, bipolar, and ganglion cells correspond to the implemented pathways. Furthermore, we show that adopting numerical integration can both accelerate retinal pathway simulations by more than 50% when compared with traditional ODE solvers in some cases, and prove to be a more realizable solution for the hardware implementation of predictive retinal models.

Visual Acuity Testing Using a Random Method Visual Acuity Application.

BACKGROUND: A visual acuity (VA) testing application for the iPad® (Apple, Cupertino, CA) tablet computer using the mirroring technique was developed that randomly presented letters categorized by cognoscibility. The aim of this study was to assess whether measurements of distance VA using this application were in agreement with existing standard clinical tests of VA in adults with normal vision. MATERIALS AND METHODS: Forty-three normally sighted subjects were tested using the Early Treatment of Diabetic Retinopathy Study (ETDRS) chart. The log minutes of arc (logMAR) VA results were compared with those from the iPad-based application, which contains a Snellen chart, a Tumbling E chart, a Landolt C chart, and a VA chart consisting of Arabic figures. After a 10-min break, subjects were retested with each test in the same order. Agreement was assessed by determining the 95% limits of agreement ± 1.96 standard deviation of the differences between tests. RESULTS: The logMAR VA showed no significant difference between the ETDRS chart and the iPad Snellen chart (p = 0.66) and iPad Arabic figure chart (p = 0.29). The logMAR VA of the ETDRS chart was significantly better than that of the iPad Tumbling E chart (p < 0.01) or iPad Landolt C chart (p < 0.01). The subjects showed chart letter memory of the ETDRS chart (p < 0.05), Tumbling E chart (p = 0.03), and Landolt C chart (p = 0.001) but not of the iPad Snellen chart (p = 0.62) and iPad Arabic figure chart (p = 0.12). CONCLUSIONS: The iPad-based application of VA charts showed similar repeatability and may be a rapid and convenient alternative to some existing measures. The mirroring technique provides portability and accessibility for VA charts.

Effect of Stimulus Waveform of Biphasic Current Pulse on Retinal Ganglion Cell Responses in Retinal Degeneration (rd1) mice.

A retinal prosthesis is being developed for the restoration of vision in patients with retinitis pigmentosa (RP) and age-related macular degeneration (AMD). Determining optimal electrical stimulation parameters for the prosthesis is one of the most important elements for the development of a viable retinal prosthesis. Here, we investigated the effects of different charge-balanced biphasic pulses with regard to their effectiveness in evoking retinal ganglion cell (RGC) responses. Retinal degeneration (rd1) mice were used (n=17). From the ex-vivo retinal preparation, retinal patches were placed ganglion cell layer down onto an 8×8 multielectrode array (MEA) and RGC responses were recorded while applying electrical stimuli. For asymmetric pulses, 1st phase of the pulse is the same with symmetric pulse but the amplitude of 2nd phase of the pulse is less than 10 µA and charge balanced condition is satisfied by lengthening the duration of the pulse. For intensities (or duration) modulation, duration (or amplitude) of the pulse was fixed to 500 µs (30 µA), changing the intensities (or duration) from 2 to 60 µA (60 to 1000 µs). RGCs were classified as response-positive when PSTH showed multiple (3~4) peaks within 400 ms post stimulus and the number of spikes was at least 30% more than that for the immediate pre-stimulus 400 ms period. RGC responses were well modulated both with anodic and cathodic phase-1st biphasic pulses. Cathodic phase-1st pulses produced significantly better modulation of RGC activity than anodic phase-1st pulses regardless of symmetry of the pulse.

Memristor-based programmable logic array (PLA) and analysis as Memristive networks.

A Memristor theorized by Chua in 1971 has the potential to dramatically influence the way electronic circuits are designed. It is a two terminal device whose resistance state is based on the history of charge flow brought about as the result of the voltage being applied across its terminals and hence can be thought of as a special case of a reconfigurable resistor. Nanoscale devices using dense and regular fabrics such as Memristor cross-bar is promising new architecture for System-on-Chip (SoC) implementations in terms of not only the integration density that the technology can offer but also both improved performance and reduced power dissipation. Memristor has the capacity to switch between high and low resistance states in a cross-bar circuit configuration. The cross-bars are formed from an array of vertical conductive nano-wires cross a second array of horizontal conductive wires. Memristors are realized at the intersection of the two wires in the array through appropriate processing technology such that any particular wire in the vertical array can be connected to a wire in the horizontal array by switching the resistance of a particular intersection to a low state while other cross-points remain in a high resistance state. However the approach introduces a number of challenges. The lack of voltage gain prevents logic being cascaded and voltage level degradation affects robustness of the operation. Moreover the cross-bars introduce sneak current paths when two or more cross points are connected through the switched Memristor. In this paper, we propose Memristor-based programmable logic array (PLA) architecture and develop an analytical model to analyze the logic level on the memristive networks. The proposed PLA architecture has 12 inputs maximum and can be cascaded for more input variables with R(off)/R(on) ratio in the range from 55 to 160 of Memristors.

Memristor-MOS analog correlator for pattern recognition system.

Emergence of new materials having significant improved properties continues to influence the formulation of novel architectures and as such new developments pave the way for innovative circuits and systems such as those required in visual imaging and recognition systems. In this paper we introduce a novel approach for the design of an analog comparator suitable for pattern matching using two Memristors as part of both the stored image data as well as that of the input signal. Our proposed comparator based on Memristor-CMOS fabrication process generates a signal indicating similarity/dissimilarity between two pattern data derived from image sensor and the corresponding Memristor-based template memory. For convenience, we also present an overview of a simplified Memristor model and hence provide simulation results for comparison with that of a conventional analog CMOS comparator.

A pulse-frequency modulation sensor using memristive-based inhibitory interconnections.

This paper proposes a programmable inhibitory interconnection network between pixels in an array of novel low-voltage Schmitt-trigger-based PFM sensors that will be of interest for future applications in memristor-based early vision processing. In addition, a new low-power inverter-based pulse-frequency modulation (PFM) design and its integration with the network is also presented. To ensure no change in the memristors conductance in the network, the CMOS imager was designed for low voltage operation. That has resulted in a significant power reduction, better than 60%, and a comparable linear dynamic range when compared to published designs in the literature. The design was performed using a 0.13 um Samsung Electronics standard CMOS process, using 0.75 V supply voltage.

Integrated memristor-MOS (M2) sensor for basic pattern matching applications.

This paper introduces an integrated sensor circuit based on an analog Memristor-MOS (M2) pattern matching building block that calculates the similarity/dissimilarity between two analog values. A new approach for a pulse-width modulation pixel image sensor compatible with the memristive-MOS matching structure is introduced allowing direct comparison between incoming and stored images. The pulsed-width encoded information from the pixels is forwarded to a matching circuitry that provides an anti-Gaussian-like comparison between the states of memristors. The non-volatile and multi-state memory characteristics of memristor, together with the related ability to be programmed at any one of the intermediate states between logic '1' and logic '0' brings us closer to the implementation of bio-machines that can eventually emulate human-like sensory functions.