Electric Field-Assisted Agglomeration of Trace Nanoparticle Impurities for Ultrahigh Purity Chemicals.

With the advancement of semiconductor manufacturing technology, the effects of trace impurities in industrial chemicals have grown significantly. In industrial processes, conventional purification methods, such as filtration and distillation, have reached their limits for removing nanoparticles from aqueous and acidic solutions. Especially, silicon and silicate are two fundamental byproducts in semiconductor fabrication processes. Assembly and subsequent removal of these materials at the nanoparticle level have been confronted with significant challenges. Therefore, it is imperative to develop technologies to effectively control and remove these impurities for next-generation manufacturing processes. In this study, we explored the use of electric field-assisted assembly to agglomerate silicate and silicon nanoparticles in industry-standard aqueous and acidic solutions. By applying an alternating current electric field, we induced dipole moments in the nanoparticles, which led to their agglomeration. Notably, nanoparticles smaller than 4 nm grew into significantly larger ones, with submicroparticle sizes exceeding 87 nm for silicate and reaching 130 nm for silicon. Through systematic analysis of the size distribution changes, we identified optimal agglomeration times of 10 min for silicate and 20 min for silicon, revealing effective agglomeration within the frequency range of 1-1000 kHz. The agglomerated particles were stable for 5 days. Our electric field-assisted approach to obtain assembled nanoparticles that can be subsequently removed by conventional purification processes holds promise for enhancing future microfabrication processes, such as semiconductor manufacturing, potentially improving the manufacturing yield and uniformity by reducing the number of trace particles that can act as defective sites.

Dislocation sink annihilating threading dislocations in strain-relaxed Si1-x Ge x layer.

We proposed a dislocation sink technology for achieving Si1-x Ge x multi-bridge-channel field-effect-transistor beyond 5 nm transistor design-rule that essentially needs an almost crystalline-defect-free Si1-x Ge x channel. A generation of a dislocation sink via H+ implantations in a strain-relaxed Si0.7Ge0.3 layer grown on a Si substrate and a following annealing almost annihilate completely misfit and threading dislocations located near the interface between a relaxed Si0.7Ge0.3 layer and a Si substrate. A real-time (continuous heating from room temperature to 600 °C) in situ high-resolution-transmission-electron-microscopy and inverse-fast-Fourier-transform image observation at 1.25 MV acceleration voltage obviously demonstrated the annihilation process between dislocation sinks and remaining misfit and threading dislocations during a thermal annealing, called the [SiI or GeI + V Si or V Ge â†’ Si1-x Ge x ] annihilation process, where SiI, GeI, V Si, and V Ge are interstitial Si, interstitial Ge, Si vacancy, and Ge vacancy, respectively. In particular, the annihilation process efficiency greatly depended on the dose of H+ implantation and annealing temperature; i.e. a maximum annihilation process efficiency achieved at 5 × 1015 atoms cm-2 and 800 °C.