ABSTRACT
Novel memory devices are essential for developing low power, fast, and accurate in-memory computing and neuromorphic engineering concepts that can compete with the conventional complementary metal-oxide-semiconductor (CMOS) digital processors. 2D semiconductors provide a novel platform for advanced semiconductors with atomic thickness, low-current operation, and capability of 3D integration. This work presents a charge-trap memory (CTM) device with a MoS2 channel where memory operation arises, thanks to electron trapping/detrapping at interface states. Transistor operation, memory characteristics, and synaptic potentiation/depression for neuromorphic applications are demonstrated. The CTM device shows outstanding linearity of the potentiation by applied drain pulses of equal amplitude. Finally, pattern recognition is demonstrated by reservoir computing where the input pattern is applied as a stimulation of the MoS2 -based CTMs, while the output current after stimulation is processed by a feedforward readout network. The good accuracy, the low current operation, and the robustness to input random bit flip makes the CTM device a promising technology for future high-density neuromorphic computing concepts.
ABSTRACT
In the last decade, the silicon nanocrystal memory technology has received widespread interests from the scientific community working in the field of non-volatile solid-state memories, considering it as a feasible candidate for the post-Flash scenario. The immunity to stress-induced leakage current and the reduction of parasitic floating-gate capacitive couplings make the nanocrystal technology very attractive, especially when considering the CMOS compatible process flow. However, many open issues still exist for its development, first of all concerning its scaling perspectives. Starting from the discussion of the basic principles of nanocrystal storage, in this paper we review the major benefits and the open challenges of the silicon nanocrystal memory technology.