Controlled formation and resistivity scaling of nickel silicide nanolines.

We demonstrate a top-down method for fabricating nickel mono-silicide (NiSi) nanolines (also referred to as nanowires) with smooth sidewalls and line widths down to 15 nm. Four-probe electrical measurements reveal that the room temperature electrical resistivity of the NiSi nanolines remains constant as the line widths are reduced to 23 nm. The resistivity at cryogenic temperatures is found to increase with decreasing line width. This finding can be attributed to electron scattering at the sidewalls and is used to deduce an electron mean free path of 6.3 nm for NiSi at room temperature. The results suggest that NiSi nanolines with smooth sidewalls are able to meet the requirements for implementation at the 22 nm technology node without degradation of device performance.

Fabrication and characterization of patterned single-crystal silicon nanolines.

This letter demonstrates a method for fabricating single-crystal Si nanolines, with rectangular cross sections and nearly atomically flat sidewalls. The high quality of these nanolines leads to superb mechanical properties, with the strain to fracture measured by nanoindentation tests exceeding 8.5% for lines of 74 nm width. A large displacement burst before fracture was observed, which is attributed to a buckling mechanism. Numerical simulations show that the critical load for buckling depends on the friction at the contact surface.

RM 8111: Development of a Prototype Linewidth Standard.

Staffs of the Semiconductor Electronics Division, the Information Technology Laboratory, and the Precision Engineering Laboratory at NIST, have developed a new generation of prototype Single-Crystal CD (Critical Dimension) Reference (SCCDRM) Materials with the designation RM 8111. Their intended use is calibrating metrology instruments that are used in semiconductor manufacturing. Each reference material is configured as a 10 mm × 11 mm silicon test-structure chip that is mounted in a 200 mm silicon carrier wafer. The fabrication of both the chip and the carrier wafer uses the type of lattice-plane-selective etching that is commonly employed in the fabrication of micro electro-mechanical systems devices. The certified CDs of the reference features are determined from Atomic Force Microscope (AFM) measurements that are referenced to high-resolution transmission-electron microscopy images that reveal the cross-section counts of lattice planes having a pitch whose value is traceable to the SI meter.