Three-Dimensional Metal-Insulator-Metal Decoupling Capacitors with Optimized ZrO2 ALD Properties for Improved Electrical and Reliability Parameters.

Embedded three-dimensional (3-D) metal-insulator-metal (MIM) decoupling capacitors with high-κ dielectric films of high capacitance and long-life time are increasingly needed on integrated chips. Towards achieving better electrical performance, there is a need for investigation into the influence of the variation in atomic layer deposition (ALD) parameters used for thin high-κ dielectric films (10 nm) made of Al2O3-doped ZrO2. This variation should always be related to the structural uniformity, the electrical characteristics, and the electrical reliability of the capacitors. This paper discusses the influence of different Zr precursor pulse times per ALD cycle and deposition temperatures (283 °C/556 K and 303 °C/576 K) with respect to the capacitance density (C-V), voltage linearity and leakage current density (I-V). Moreover, the dielectric breakdown and TDDB characteristics are evaluated under a wide range of temperatures (223-423 K).

A FeFET with a novel MFMFIS gate stack: towards energy-efficient and ultrafast NVMs for neuromorphic computing.

The discovery of ferroelectricity in the fluorite structure based hafnium oxide (HfO2) material sparked major efforts for reviving the ferroelectric field effect transistor (FeFET) memory concept. A Novel metal-ferroelectric-metal-ferroelectric-insulator-semiconductor (MFMFIS) FeFET memory is reported based on dual ferroelectric integration as an MFM and MFIS in a single gate stack using Si-doped Hafnium oxide (HSO) ferroelectric (FE) material. The MFMFIS top and bottom electrode contacts, dual HSO based ferroelectric layers, and tailored MFM to MFIS area ratio (AR-TB) provide a flexible stack structure tuning for improving the FeFET performance. The AR-TB tuning shows a tradeoff between the MFM voltage increase and the weaker FET Si channel inversion, particularly notable in the drain saturation currentID(sat)when the AR-TB ratio decreases. Dual HSO ferroelectric layer integration enables a maximized memory window (MW) and dynamic control of its size by tuning the MFM to MFIS switching contribution through the AR-TB change. The stack structure control via the AR-TB tuning shows further merits in terms of a low voltage switching for a saturated MW size, an extremely linear at wide dynamic range of the current update, as well as high symmetry in the long term synaptic potentiation and depression. The MFMFIS stack reliability is reported in terms of the switching variability, temperature dependence, endurance, and retention. The MFMFIS concept is thoroughly discussed revealing profound insights on the optimal MFMFIS stack structure control for enhancing the FeFET memory performance.

Structural and Dielectric Properties of Subnanometric Laminates of Binary Oxides.

Capacitors with a dielectric material consisting of amorphous laminates of Al2O3 and TiO2 with subnanometer individual layer thicknesses can show strongly enhanced capacitance densities compared to the bulk or laminates with nanometer layer thickness. In this study, the structural and dielectric properties of such subnanometer laminates grown on silicon by state-of-the-art atomic layer deposition are investigated with varying electrode materials. The laminates show a dielectric constant reaching 95 combined with a dielectric loss (tan δ) of about 0.2. The differences of the observed dielectric properties in capacitors with varying electrodes indicate that chemical effects at the interface with the TiN electrode play a major role, while the influence of the local roughness of the individual layers is rather limited.

SiGe epitaxy on a 300 mm batch furnace.

This work reports the feasibility of silicon and silicon germanium epitaxy using an ASM A412(TMa) LPCVD all quartz, hot wall, vertical batch furnace reactor using 100 wafer product loads. The very same furnace can be used for 25 wafer and 200 wafer load size, without any hardware changes, dependant on production needs. Following this approach a significant cost reduction for epitaxy in 300 mm high volume manufacturing is possible and enables new applications. The native oxide of the substrate was removed by wet chemical cleaning with time coupling of less than 1 h and subsequent in-situ low pressure hydrogen anneal prior to Si or SiGe deposition. The epitaxial layers were grown using silane and germane. The Si and SiGe layers have been characterized with ToFSIMS, XRD, Raman, AFM and TEM confirming excellent crystalline quality, layer thickness and within wafer SiGe stoichiometry uniformity.