An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage.

The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC.

Chalcogenide Ovonic Threshold Switching Selector.

Today's explosion of data urgently requires memory technologies capable of storing large volumes of data in shorter time frames, a feat unattainable with Flash or DRAM. Intel Optane, commonly referred to as three-dimensional phase change memory, stands out as one of the most promising candidates. The Optane with cross-point architecture is constructed through layering a storage element and a selector known as the ovonic threshold switch (OTS). The OTS device, which employs chalcogenide film, has thereby gathered increased attention in recent years. In this paper, we begin by providing a brief introduction to the discovery process of the OTS phenomenon. Subsequently, we summarize the key electrical parameters of OTS devices and delve into recent explorations of OTS materials, which are categorized as Se-based, Te-based, and S-based material systems. Furthermore, we discuss various models for the OTS switching mechanism, including field-induced nucleation model, as well as several carrier injection models. Additionally, we review the progress and innovations in OTS mechanism research. Finally, we highlight the successful application of OTS devices in three-dimensional high-density memory and offer insights into their promising performance and extensive prospects in emerging applications, such as self-selecting memory and neuromorphic computing.

Imaging the Three-Dimensional Conductive Channel in Filamentary-Based Oxide Resistive Switching Memory.

Filamentary-based oxide resistive memory is considered as a disruptive technology for nonvolatile data storage and reconfigurable logic. Currently accepted models explain the resistive switching in these devices through the presence/absence of a conductive filament (CF) that is described as a reversible nanosized valence-change in an oxide material. During device operation, the CF cycles billion of times at subnanosecond speed, using few tens of microamperes as operating current and thus determines the whole device's performance. Despite its importance, the CF observation is hampered by the small filament size and its minimal compositional difference with the surrounding material. Here we show an experimental solution to this problem and provide the three-dimensional (3D) characterization of the CF in a scaled device. For this purpose we have recently developed a tomography technique which combines the high spatial resolution of scanning probe microscopy with subnanometer precision in material removal, leading to a true 3D-probing metrology concept. We locate and characterize in three-dimensions the nanometric volume of the conductive filament in state-of-the-art bipolar oxide-based devices. Our measurements demonstrate that the switching occurs through the formation of a single conductive filament. The filaments exhibit sizes below 10 nm and present a constriction near the oxygen-inert electrode. Finally, different atomic-size contacts are observed as a function of the programming current, providing evidence for the filament's nature as a defects modulated quantum contact.

Understanding the Dual Nature of the Filament Dissolution in Conductive Bridging Devices.

The formation and rupture of conductive filaments (CFs) inside an insulating medium is used as hardware encoding of the state of a memory cell ("1" - "0") in filamentary-based conductive bridging memories. Currently accepted models explain the filament erase (reset) as the subtraction of conductive metal atoms from the CF; however, they do not fully account for the rich set of phenomena experimentally observed during the reset. The details of the filament erase are unraveled on the nanometer scale by means of an atomic force microscopy-based tomography technique enabling the 3D observation of erased CFs. "Non-broken" and "broken" CFs are observed, whereby the increase in resistance originates, respectively, from a constriction point in the current path and from an interrupted CF. We demonstrate that their existence and morphology can be related to the specific formation history of the CF, and we identify the physical volume of the CF as being mainly responsible for the type of filament erase.