Dark-field optical fault inspection of ∼10 nm scale room-temperature silicon single-electron transistors.

Dark-field (DF) optical microscopy, combined with optical simulation based on modal diffraction theory for transverse electric polarized white light, is shown to provide non-invasive, sub-wavelength geometrical information for nanoscale etched device structures. Room temperature (RT) single electron transistors (SETs) in silicon, defined using etched ∼10 nm point-contacts (PCs) and in-plane side gates, are investigated to enable fabrication fault detection. Devices are inspected using scanning electron microscopy, bright-field (BF) and DF imaging. Compared to BF, DF imaging enhances contrast from edge diffraction by ×3.5. Sub-wavelength features in the RT SET structure lead to diffraction peaks in the DF intensity patterns, creating signatures for device geometry. These features are investigated using a DF line scan optical simulation approximation of the experimental results. Dark field imaging and simulation are applied to three types of structures, comprising successfully-fabricated, over-etched and interconnected PC/gate devices. Each structure can be identified via DF signatures, providing a non-invasive fault detection method to investigate etched nanodevice morphology.

Fast turnaround fabrication of silicon point-contact quantum-dot transistors using combined thermal scanning probe lithography and laser writing.

The fabrication of high-performance solid-state silicon quantum-devices requires high resolution patterning with minimal substrate damage. We have fabricated room temperature (RT) single-electron transistors (SETs) based on point-contact tunnel junctions using a hybrid lithography tool capable of both high resolution thermal scanning probe lithography and high throughput direct laser writing. The best focal z-position and the offset of the tip- and the laser-writing positions were determined in situ with the scanning probe. We demonstrate <100 nm precision in the registration between the high resolution and high throughput lithographies. The SET devices were fabricated on degenerately doped n-type >1020/cm3 silicon on insulator chips using a CMOS compatible geometric oxidation process. The characteristics of the three devices investigated were dominated by the presence of Si nanocrystals or phosphorous atoms embedded within the SiO2, forming quantum dots (QDs). The small size and strong localisation of electrons on the QDs facilitated SET operation even at RT. Temperature measurements showed that in the range 300 K > T > âˆ¼100 K, the current flow was thermally activated but at <100 K, it was dominated by tunnelling.

Excited states and quantum confinement in room temperature few nanometre scale silicon single electron transistors.

Single nanometre scale quantum dots (QDs) have significant potential for many 'beyond CMOS' nanoelectronics and quantum computation applications. The fabrication and measurement of few nanometre silicon point-contact QD single-electron transistors are reported, which both operate at room temperature (RT) and are fabricated using standard processes. By combining thin silicon-on-insulator wafers, specific device geometry, and controlled oxidation, <10 nm nanoscale point-contact channels are defined. In this limit of the point-contact approach, ultra-small, few nanometre scale QDs are formed, enabling RT measurement of the full QD characteristics, including excited states to be made. A remarkably large QD electron addition energy ∼0.8 eV, and a quantum confinement energy ∼0.3 eV, are observed, implying a QD only ∼1.6 nm in size. In measurements of 19 RT devices, the extracted QD radius lies within a narrow band, from 0.8 to 2.35 nm, emphasising the single-nanometre scale of the QDs. These results demonstrate that with careful control, 'beyond CMOS' RT QD transistors can be produced using current 'conventional' semiconductor device fabrication techniques.

Single-electron and quantum confinement limits in length-scaled silicon nanowires.

Quantum-effects will play an important role in both future CMOS and 'beyond CMOS' technologies. By comparing single-electron transistors formed in un-patterned, uniform-width silicon nanowire (SiNW) devices with core widths from ∼5-40 nm, and gated lengths of 1 µm and ∼50 nm, we show conditions under which these effects become significant. Coulomb blockade drain-source current-voltage characteristics, and single-electron current oscillations with gate voltage have been observed at room temperature. Detailed electrical characteristics have been measured from 8-300 K. We show that while shortening the nanowire gate length to 50 nm reduces the likelihood of quantum dots to only a few, it increases their influence on the electrical characteristics. This highlights explicitly both the significance of quantum effects for understanding the electrical performance of nominally 'classical' SiNW devices and also their potential for new quantum effect 'beyond CMOS' devices.