Improvements in 2D p-type WSe2 transistors towards ultimate CMOS scaling.

This paper provides comprehensive experimental analysis relating to improvements in the two-dimensional (2D) p-type metal-oxide-semiconductor (PMOS) field effect transistors (FETs) by pure van der Waals (vdW) contacts on few-layer tungsten diselenide (WSe2) with high-k metal gate (HKMG) stacks. Our analysis shows that standard metallization techniques (e.g., e-beam evaporation at moderate pressure ~ 10-5 torr) results in significant Fermi-level pinning, but Schottky barrier heights (SBH) remain small (< 100 meV) when using high work function metals (e.g., Pt or Pd). Temperature-dependent analysis uncovers a more dominant contribution to contact resistance from the channel access region and confirms significant improvement through less damaging metallization techniques (i.e., reduced scattering) combined with strongly scaled HKMG stacks (enhanced carrier density). A clean contact/channel interface is achieved through high-vacuum evaporation and temperature-controlled stepped deposition providing large improvements in contact resistance. Our study reports low contact resistance of 5.7 kΩ-µm, with on-state currents of ~ 97 µA/µm and subthreshold swing of ~ 140 mV/dec in FETs with channel lengths of 400 nm. Furthermore, theoretical analysis using a Landauer transport ballistic model for WSe2 SB-FETs elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance (excellent on-state current vs subthreshold swing benchmarks) towards the ultimate CMOS scaling limit.

Analysis of Schottky barrier heights and reduced Fermi-level pinning in monolayer CVD-grown MoS2field-effect-transistors.

Chemical vapor deposition (CVD)-grown monolayer (ML) molybdenum disulfide (MoS2) is a promising material for next-generation integrated electronic systems due to its capability of high-throughput synthesis and compatibility with wafer-scale fabrication. Several studies have described the importance of Schottky barriers in analyzing the transport properties and electrical characteristics of MoS2field-effect-transistors (FETs) with metal contacts. However, the analysis is typically limited to single devices constructed from exfoliated flakes and should be verified for large-area fabrication methods. In this paper, CVD-grown ML MoS2was utilized to fabricate large-area (1 cm × 1 cm) FET arrays. Two different types of metal contacts (i.e. Cr/Au and Ti/Au) were used to analyze the temperature-dependent electrical characteristics of ML MoS2FETs and their corresponding Schottky barrier characteristics. Statistical analysis provides new insight about the properties of metal contacts on CVD-grown MoS2compared to exfoliated samples. Reduced Schottky barrier heights (SBH) are obtained compared to exfoliated flakes, attributed to a defect-induced enhancement in metallization of CVD-grown samples. Moreover, the dependence of SBH on metal work function indicates a reduction in Fermi level pinning compared to exfoliated flakes, moving towards the Schottky-Mott limit. Optical characterization reveals higher defect concentrations in CVD-grown samples supporting a defect-induced metallization enhancement effect consistent with the electrical SBH experiments.

Room-Temperature Synthesis of 2D Janus Crystals and their Heterostructures.

Janus crystals represent an exciting class of 2D materials with different atomic species on their upper and lower facets. Theories have predicted that this symmetry breaking induces an electric field and leads to a wealth of novel properties, such as large Rashba spin-orbit coupling and formation of strongly correlated electronic states. Monolayer MoSSe Janus crystals have been synthesized by two methods, via controlled sulfurization of monolayer MoSe2 and via plasma stripping followed thermal annealing of MoS2 . However, the high processing temperatures prevent growth of other Janus materials and their heterostructures. Here, a room-temperature technique for the synthesis of a variety of Janus monolayers with high structural and optical quality is reported. This process involves low-energy reactive radical precursors, which enables selective removal and replacement of the uppermost chalcogen layer, thus transforming classical transition metal dichalcogenides into a Janus structure. The resulting materials show clear mixed character for their excitonic transitions, and more importantly, the presented room-temperature method enables the demonstration of first vertical and lateral heterojunctions of 2D Janus TMDs. The results present significant and pioneering advances in the synthesis of new classes of 2D materials, and pave the way for the creation of heterostructures from 2D Janus layers.