Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.

Analog in-memory computing-a promising approach for energy-efficient acceleration of deep learning workloads-computes matrix-vector multiplications but only approximately, due to nonidealities that often are non-deterministic or nonlinear. This can adversely impact the achievable inference accuracy. Here, we develop an hardware-aware retraining approach to systematically examine the accuracy of analog in-memory computing across multiple network topologies, and investigate sensitivity and robustness to a broad set of nonidealities. By introducing a realistic crossbar model, we improve significantly on earlier retraining approaches. We show that many larger-scale deep neural networks-including convnets, recurrent networks, and transformers-can in fact be successfully retrained to show iso-accuracy with the floating point implementation. Our results further suggest that nonidealities that add noise to the inputs or outputs, not the weights, have the largest impact on accuracy, and that recurrent networks are particularly robust to all nonidealities.

Optimised weight programming for analogue memory-based deep neural networks.

Analogue memory-based deep neural networks provide energy-efficiency and per-area throughput gains relative to state-of-the-art digital counterparts such as graphics processing units. Recent advances focus largely on hardware-aware algorithmic training and improvements to circuits, architectures, and memory devices. Optimal translation of software-trained weights into analogue hardware weights-given the plethora of complex memory non-idealities-represents an equally important task. We report a generalised computational framework that automates the crafting of complex weight programming strategies to minimise accuracy degradations during inference, particularly over time. The framework is agnostic to network structure and generalises well across recurrent, convolutional, and transformer neural networks. As a highly flexible numerical heuristic, the approach accommodates arbitrary device-level complexity, making it potentially relevant for a variety of analogue memories. By quantifying the limit of achievable inference accuracy, it also enables analogue memory-based deep neural network accelerators to reach their full inference potential.

An ELIME assay for hepatitis A virus detection.

An Enzyme Linked ImmunoMagnetic Electrochemical assay (ELIME) was developed for the detection of the hepatitis A virus (HAV). This system is based on the use of new polydopamine-modified magnetic nanobeads as solid support for the immunochemical chain, and an array of 8 screen-printed electrodes as a sensing platform. Enzymatic-by-product is quickly measured by differential pulse voltammetry. For this purpose, all analytical parameters were optimized; in particular, different blocking reagents were evaluated in order to minimize the nonspecific interaction of bioreagents. Using the ELIME assays, a quantitative determination of HAV can be achieved with a detection limit of 1·10-11 IU mL-1 and a working range between 10-10 - 5 × 10-7 IU mL-1. The cross-reactivity of the commercial monoclonal antibodies against HAV used in ELIME assays was tested for Coxsackie B4, resulting very low. The sensitivity was also investigated and compared with spectrophotometric sandwich ELISA. The average relative standard deviation (RSD) of the ELIME method was less than 5% for the assays performed on the same day, and 7% for the measurements made on different days. The proposed system was applied to the cell culture of HAV, which title was quantified by Real-Time Quantitative Reverse Transcription PCR (RT¬qPCR). To compare the results, a correlation between the units used in ELIME (IU mL-1) and those used in RT¬qPCR (genome mL-1) was established using a HAV-positive sample, resulting in 1 IU mL-1-10-4 gen mL-1 (R2 = 0.978). The ELIME tool exhibits good stability and high biological selectivity for HAV antigen detection and was successfully applied for the determination of HAV in tap water.

Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices.

Recent advances in deep learning have been driven by ever-increasing model sizes, with networks growing to millions or even billions of parameters. Such enormous models call for fast and energy-efficient hardware accelerators. We study the potential of Analog AI accelerators based on Non-Volatile Memory, in particular Phase Change Memory (PCM), for software-equivalent accurate inference of natural language processing applications. We demonstrate a path to software-equivalent accuracy for the GLUE benchmark on BERT (Bidirectional Encoder Representations from Transformers), by combining noise-aware training to combat inherent PCM drift and noise sources, together with reduced-precision digital attention-block computation down to INT6.

Self-aligned coupled nanowire transistor.

The integration of multiple functionalities into individual nanoelectronic components is increasingly explored as a means to step up computational power, or for advanced signal processing. Here, we report the fabrication of a coupled nanowire transistor, a device where two superimposed high-performance nanowire field-effect transistors capable of mutual interaction form a thyristor-like circuit. The structure embeds an internal level of signal processing, showing promise for applications in analogue computation. The device is naturally derived from a single NW via a self-aligned fabrication process.

Top-gated silicon nanowire transistors in a single fabrication step.

Top-gated silicon nanowire transistors are fabricated by preparing all terminals (source, drain, and gate) on top of the nanowire in a single step via dose-modulated e-beam lithography. This outperforms other time-consuming approaches requiring alignment of multiple patterns, where alignment tolerances impose a limit on device scaling. We use as gate dielectric the 10-15 nm SiO(2) shell naturally formed during vapor-transport growth of Si nanowires, so the wires can be implemented into devices after synthesis without additional processing. This natural oxide shell has negligible leakage over the operating range. Our single-step patterning is a most practical route for realization of short-channel nanowire transistors and can be applied to a number of nanodevice geometries requiring nonequivalent electrodes.

Ion beam doping of silicon nanowires.

We demonstrate n- and p-type field-effect transistors based on Si nanowires (SiNWs) implanted with P and B at fluences as high as 10(15) cm (-2). Contrary to what would happen in bulk Si for similar fluences, in SiNWs this only induces a limited amount of amorphization and structural disorder, as shown by electrical transport and Raman measurements. We demonstrate that a fully crystalline structure can be recovered by thermal annealing at 800 degrees C. For not-annealed, as-implanted NWs, we correlate the onset of amorphization with an increase of phonon confinement in the NW core. This is ion-dependent and detectable for P-implantation only. Hysteresis is observed following both P and B implantation.

Nanowire lithography on silicon.

Nanowire lithography (NWL) uses nanowires (NWs), grown and assembled by chemical methods, as etch masks to transfer their one-dimensional morphology to an underlying substrate. Here, we show that SiO2 NWs are a simple and compatible system to implement NWL on crystalline silicon and fabricate a wide range of architectures and devices. Planar field-effect transistors made of a single SOI-NW channel exhibit a contact resistance below 20 kOmega and scale with the channel width. Further, we assess the electrical response of NW networks obtained using a mask of SiO2 NWs ink-jetted from solution. The resulting conformal network etched into the underlying wafer is monolithic, with single-crystalline bulk junctions; thus no difference in conductivity is seen between a direct NW bridge and a percolating network. We also extend the potential of NWL into the third dimension, by using a periodic undercutting that produces an array of vertically stacked NWs from a single NW mask.