A ferroelectric fin diode for robust non-volatile memory.

Among today's nonvolatile memories, ferroelectric-based capacitors, tunnel junctions and field-effect transistors (FET) are already industrially integrated and/or intensively investigated to improve their performances. Concurrently, because of the tremendous development of artificial intelligence and big-data issues, there is an urgent need to realize high-density crossbar arrays, a prerequisite for the future of memories and emerging computing algorithms. Here, a two-terminal ferroelectric fin diode (FFD) in which a ferroelectric capacitor and a fin-like semiconductor channel are combined to share both top and bottom electrodes is designed. Such a device not only shows both digital and analog memory functionalities but is also robust and universal as it works using two very different ferroelectric materials. When compared to all current nonvolatile memories, it cumulatively demonstrates an endurance up to 1010 cycles, an ON/OFF ratio of ~102, a feature size of 30 nm, an operating energy of ~20 fJ and an operation speed of 100 ns. Beyond these superior performances, the simple two-terminal structure and their self-rectifying ratio of ~ 104 permit to consider them as new electronic building blocks for designing passive crossbar arrays which are crucial for the future in-memory computing.

Ultralow-power in-memory computing based on ferroelectric memcapacitor network.

Analog storage through synaptic weights using conductance in resistive neuromorphic systems and devices inevitably generates harmful heat dissipation. This thermal issue not only limits the energy efficiency but also hampers the very-large-scale and highly complicated hardware integration as in the human brain. Here we demonstrate that the synaptic weights can be simulated by reconfigurable non-volatile capacitances of a ferroelectric-based memcapacitor with ultralow-power consumption. The as-designed metal/ferroelectric/metal/insulator/semiconductor memcapacitor shows distinct 3-bit capacitance states controlled by the ferroelectric domain dynamics. These robust memcapacitive states exhibit uniform maintenance of more than 104 s and well endurance of 109 cycles. In a wired memcapacitor crossbar network hardware, analog vector-matrix multiplication is successfully implemented to classify 9-pixel images by collecting the sum of displacement currents (I = C × dV/dt) in each column, which intrinsically consumes zero energy in memcapacitors themselves. Our work sheds light on an ultralow-power neural hardware based on ferroelectric memcapacitors.

Ferroelectric-defined reconfigurable homojunctions for in-memory sensing and computing.

Recently, the increasing demand for data-centric applications is driving the elimination of image sensing, memory and computing unit interface, thus promising for latency- and energy-strict applications. Although dedicated electronic hardware has inspired the development of in-memory computing and in-sensor computing, folding the entire signal chain into one device remains challenging. Here an in-memory sensing and computing architecture is demonstrated using ferroelectric-defined reconfigurable two-dimensional photodiode arrays. High-level cognitive computing is realized based on the multiplications of light power and photoresponsivity through the photocurrent generation process and Kirchhoff's law. The weight is stored and programmed locally by the ferroelectric domains, enabling 51 (>5 bit) distinguishable weight states with linear, symmetric and reversible manipulation characteristics. Image recognition can be performed without any external memory and computing units. The three-in-one paradigm, integrating high-level computing, weight memorization and high-performance sensing, paves the way for a computing architecture with low energy consumption, low latency and reduced hardware overhead.

A Sub-10 nm Vertical Organic/Inorganic Hybrid Transistor for Pain-Perceptual and Sensitization-Regulated Nociceptor Emulation.

Pain-perceptual nociceptors (PPN) are essential sensory neurons that recognize harmful stimuli and can empower the human body to react appropriately and perceive precisely unusual or dangerous conditions in the real world. Furthermore, the sensitization-regulated nociceptors (SRN) can greatly assist pain-sensitive human to reduce pain sensation by normalizing hyperexcitable central neural activity. Therefore, the implementation of PPNs and SRNs in hardware using emerging nanoscale devices can greatly improve the efficiency of bionic medical machines by giving them different sensitivities to external stimuli according to different purposes. However, current most-normal organic/oxide transistors face a great challenge due to channel scaling, especially in the sub-10 nm channel technology. Here, a sub-10 nm indium-tin-oxide transistor with an ultrashort vertical channel as low as ≈3 nm, using sodium alginate bio-polymer electrolyte as gate dielectric, is demonstrated. This device can emulate important characteristics of PPN such as pain threshold, memory of prior injury, and pain sensitization/desensitization. Furthermore, the most intriguing character of SRN can be achieved by tuning the channel thickness. The proposed device can open new avenues for the fascinating applications of next-generation neuromorphic brain-like systems, such as bio-inspired electronic skins and humanoid robots.