A Composite-Type MEMS Pirani Gauge for Wide Range and High Accuracy.

To achieve a wide range and high accuracy detection of the vacuum level, for example, in an encapsulated vacuum microcavity, a composite-type MEMS Pirani gauge has been designed and fabricated. The Pirani gauge consists of two gauges of different sizes connected in series, with one gauge having a larger heat-sensitive area and a larger air gap for extending the lower measurable limit of pressure (i.e., the high vacuum end) and the other gauge having a smaller heat-sensitive area and a smaller air gap for extending the upper measurable limit. The high-resistivity titanium metal was chosen as the thermistor; SiNx was chosen as the dielectric layer, considering the factors relevant to simulation and manufacturing. By simulation using COMSOL Multiphysics and NI Multisim, a range of measurement of 2 × 10-2 to 2 × 105 Pa and a sensitivity of 52.4 mV/lgPa were obtained in an N2 environment. The performance of the fabricated Pirani gauge was evaluated by using an in-house made vacuum test system. In the test, the actual points of measurement range from 6.6 × 10-2 to 1.12 × 105 Pa, and the highest sensitivity is up to 457.6 mV/lgPa. The experimental results are better in the range of measurement, sensitivity, and accuracy than the simulation results. The Pirani gauge proposed in this study is simple in structure, easy to manufacture, and suitable for integration with other MEMS devices in a microcavity to monitor the vacuum level therein.

Design of a High Sensitivity Pirani Gauge Based on Vanadium Oxide Film for High Vacuum Measurement.

We have designed a hot-plate-type micro-Pirani vacuum gauge with a simple structure and compatibility with conventional semiconductor fabrication processes. In the Pirani gauge, we used a vanadium oxide (VOx) membrane as the thermosensitive component, taking advantage of the high temperature coefficient of resistance (TCR) of VOx. The TCR value of VOx is -2%K-1∼-3%K-1, an order of magnitude higher than those of other thermal-sensitive materials, such as platinum and titanium (0.3%K-1∼0.4%K-1). On one hand, we used the high TCR of VOx to increase the Pirani sensitivity. On the other hand, we optimized the floating structure to decrease the thermal conductivity so that the detecting range of the Pirani gauge was extended on the low-pressure end. We carried out simulation experiments on the thermal zone of the Pirani gauge, the width of the cantilever beam, the material and thickness of the supporting layer, the thickness of the thermal layer (VOx), the depth of the cavity, and the shape and size. Finally, we decided on the basic size of the Pirani gauge. The prepared Pirani gauge has a thermal sensitive area of 130 × 130 µm2, with a cantilever width of 13 µm, cavity depth of 5 µm, supporting layer thickness of 300 nm, and VOx layer thickness of 110 nm. It has a dynamic range of 10-1~104 Pa and a sensitivity of 1.23 V/lgPa. The VOx Pirani was designed using a structure and fabrication process compatible with a VOx-based uncooled infrared microbolometer so that it can be integrated by wafer level. This work contains only our MEMS Pirani gauge device design, preparation process design, and readout circuit design, while the characterization and relevant experimental results will be reported in the future.

Structural Optimization and Mechanical Simulation of MEMS Thin-Film Getter-Heater Unit.

A MEMS thin-film getter-heater unit has been previously proposed for the vacuum packaging of a Micro-Electro-Mechanical System (MEMS) device, where the floating structure (FS) design is found to be obviously more power-efficient than the solid structure (SS) one by heat transfer capacity simulation. However, the mechanical strength of the FS is weaker than the SS by nature. For high temperature usage, the unit structure must be optimized in order to avoid fracture of the cantilever beam or film delamination due to strong excessive stress caused by heating. In this paper, COMSOL is used to simulate the stress and deformation of the MEMS thin-film getter-heater unit with the cantilever structure. By comparing various cantilever structures, it is found that a model with a symmetrically-shaped heater and edge-center-located cantilever model (II-ECLC model) is the most suitable. In this model, even when the structure is heated to about 600 °C, the maximum stress of the cantilever beam is only 455 MPa, much lower than the tensile strength of silicon nitride (Si3N4, 12 GPa), and the maximum deformation displacement is about 200 µm. Meanwhile, the interfacial stress between the getter and the insulating layer is 44 MPa, sufficiently lower than the adhesion strength between silicon nitride film and titanium film (400-1850 MPa). It is further found that both the stress of the cantilever structure and the interfacial stress between the getter and the insulating layer beneath increase linearly with temperature; and the deformation of the cantilever structure is proportional to its stress. This work gives guidance on the design of MEMS devices with cantilever structures and works in high temperature situations.

Process Optimization and Performance Evaluation of TSV Arrays for High Voltage Application.

In order to obtain high-quality through-silicon via (TSV) arrays for high voltage applications, we optimized the fabrication processes of the Si holes, evaluated the dielectric layers, carried out hole filling by Cu plating, and detected the final structure and electric properties of the TSVs. The Si through-hole array was fabricated in an 8-inch Si substrate as follows: First, a blind Si hole array was formed by the Si deep reactive etching (DRIE) technique using the Bosch process, but with the largest width of the top scallops reduced to 540 nm and the largest notch elimidiameternated by backside grinding, which also opens the bottom ends of the Si blind holes and forms 500-µm-deep Si through holes. Then, the sidewalls of the Si holes were further smoothed by a combination of thermal oxidation and wet etching of the thermal oxide. The insulating capability of the dielectric layers was evaluated prior to metal filling by using a test kit. The metal filling of the through holes was carried out by bottom-up Cu electroplating and followed by annealing at 300 °C for 1 h to release the electroplating stress and to prevent possible large metal thermal expansion in subsequent high-temperature processes. The TSV arrays with different hole diameters and spacing were detected: no visible defects or structure peeling was found by scanning electron microscopy (SEM) observations, and no detectable interdiffusion between Cu and the dielectric layers was detected by energy dispersive X-ray (EDX) analyses. Electric tests indicated that the leakage currents between two adjacent TSVs were as low as 6.80 × 10-10 A when a DC voltage was ramped up from 0 to 350 V, and 2.86 × 10-9 A after a DC voltage was kept at 100 V for 200 s.