Fidelity benchmarks for two-qubit gates in silicon.

Universal quantum computation will require qubit technology based on a scalable platform1, together with quantum error correction protocols that place strict limits on the maximum infidelities for one- and two-qubit gate operations2,3. Although various qubit systems have shown high fidelities at the one-qubit level4-10, the only solid-state qubits manufactured using standard lithographic techniques that have demonstrated two-qubit fidelities near the fault-tolerance threshold6 have been in superconductor systems. Silicon-based quantum dot qubits are also amenable to large-scale fabrication and can achieve high single-qubit gate fidelities (exceeding 99.9 per cent) using isotopically enriched silicon11,12. Two-qubit gates have now been demonstrated in a number of systems13-15, but as yet an accurate assessment of their fidelities using Clifford-based randomized benchmarking, which uses sequences of randomly chosen gates to measure the error, has not been achieved. Here, for qubits encoded on the electron spin states of gate-defined quantum dots, we demonstrate Bell state tomography with fidelities ranging from 80 to 89 per cent, and two-qubit randomized benchmarking with an average Clifford gate fidelity of 94.7 per cent and an average controlled-rotation fidelity of 98 per cent. These fidelities are found to be limited by the relatively long gate times used here compared with the decoherence times of the qubits. Silicon qubit designs employing fast gate operations with high Rabi frequencies16,17, together with advanced pulsing techniques18, should therefore enable much higher fidelities in the near future.

Integrated silicon qubit platform with single-spin addressability, exchange control and single-shot singlet-triplet readout.

Silicon quantum dot spin qubits provide a promising platform for large-scale quantum computation because of their compatibility with conventional CMOS manufacturing and the long coherence times accessible using 28Si enriched material. A scalable error-corrected quantum processor, however, will require control of many qubits in parallel, while performing error detection across the constituent qubits. Spin resonance techniques are a convenient path to parallel two-axis control, while Pauli spin blockade can be used to realize local parity measurements for error detection. Despite this, silicon qubit implementations have so far focused on either single-spin resonance control, or control and measurement via voltage-pulse detuning in the two-spin singlet-triplet basis, but not both simultaneously. Here, we demonstrate an integrated device platform incorporating a silicon metal-oxide-semiconductor double quantum dot that is capable of single-spin addressing and control via electron spin resonance, combined with high-fidelity spin readout in the singlet-triplet basis.