On-chip integrated quantum emitter with 'trap-enhance-guide': a simulation approach.

To address the challenges of developing a scalable system of an on-chip integrated quantum emitter, we propose to leverage the loss in our hybrid plasmonic-photonic structure to simultaneously achieve Purcell enhancement as well as on-chip maneuvering of nanoscale emitter via optical trapping with guided excitation-emission routes. In this report, we have analyzed the feasibility of the functional goals of our proposed system in the metric of trapping strength (∼8KBT), Purcell factor (>1000∼), and collection efficiency (∼10%). Once realized, the scopes of the proposed device can be advanced to develop a scalable platform for integrated quantum technology.

Optimizing epsilon-near-zero based plasmon assisted modulators through surface-to-volume ratio.

Plasmonic-based integrated nanophotonic modulators, despite their promising features, have one key limiting factor of large insertion loss (IL), which limits their practical potential. To combat this, we utilize a plasmon-assisted approach through the lens of surface-to-volume ratio to realize a 4-slot based EAM with an extinction ratio (ER) of 2.62 dB/µm and insertion loss (IL) of 0.3 dB/µm operating at ∼1 GHz and a single slot design with ER of 1.4 dB/µm and IL of 0.25 dB/µm operating at ∼20 GHz, achieved by replacing the traditional metal contact with heavily doped indium tin oxide (ITO). Furthermore, our analysis imposes realistic fabrication constraints, and material properties, and illustrates trade-offs in the performance that must be carefully optimized for a given scenario.