Integrated bioelectronic proton-gated logic elements utilizing nanoscale patterned Nafion.

A central endeavour in bioelectronics is the development of logic elements to transduce and process ionic to electronic signals. Motivated by this challenge, we report fully monolithic, nanoscale logic elements featuring n- and p-type nanowires as electronic channels that are proton-gated by electron-beam patterned Nafion. We demonstrate inverter circuits with state-of-the-art ion-to-electron transduction performance giving DC gain exceeding 5 and frequency response up to 2 kHz. A key innovation facilitating the logic integration is a new electron-beam process for patterning Nafion with linewidths down to 125 nm. This process delivers feature sizes compatible with low voltage, fast switching elements. This expands the scope for Nafion as a versatile patternable high-proton-conductivity element for bioelectronics and other applications requiring nanoengineered protonic membranes and electrodes.

A parylene coating system specifically designed for producing ultra-thin films for nanoscale device applications.

We report on a parylene chemical vapor deposition system custom designed for producing ultrathin parylene films (5-100 nm thickness) for use as an electrical insulator in nanoscale electronic devices, including as the gate insulator in transistors. The system features a small deposition chamber that can be isolated and purged for process termination, a quartz crystal microbalance for monitoring deposition, and a rotating angled stage to increase coating conformity. The system was mostly built from off-the-shelf vacuum fittings allowing for easy modification and reduced cost compared to commercial parylene coating systems. The production of ultrathin parylene films for device applications is a niche not well catered to by commercial coating systems, which are typically designed to give thicker coatings (microns) with high uniformity over much larger areas. An added advantage of our design for nanoscale device applications is that the small deposition chamber is readily removable for transfer to a glovebox to enable parylene deposition onto pristine surfaces prepared in oxygen/water-free environments with minimal contamination.

Regaining a Spatial Dimension: Mechanically Transferrable Two-Dimensional InAs Nanofins Grown by Selective Area Epitaxy.

We report a method for growing rectangular InAs nanofins with deterministic length, width, and height by dielectric-templated selective-area epitaxy. These freestanding nanofins can be transferred to lay flat on a separate substrate for device fabrication. A key goal was to regain a spatial dimension for device design compared to nanowires, while retaining the benefits of bottom-up epitaxial growth. The transferred nanofins were made into devices featuring multiple contacts for Hall effect and four-terminal resistance studies, as well as a global back-gate and nanoscale local top-gates for density control. Hall studies give a 3D electron density 2.5-5 × 1017 cm-3, corresponding to an approximate surface accumulation layer density 3-6 × 1012 cm-2 that agrees well with previous studies of InAs nanowires. We obtain Hall mobilities as high as 1200 cm2/(V s), field-effect mobilities as high as 4400 cm2/(V s), and clear quantum interference structure at temperatures as high as 20 K. Our devices show excellent prospects for fabrication into more complicated devices featuring multiple ohmic contacts, local gates, and possibly other functional elements, for example, patterned superconductor contacts, that may make them attractive options for future quantum information applications.

Achieving short high-quality gate-all-around structures for horizontal nanowire field-effect transistors.

We introduce a fabrication method for gate-all-around nanowire field-effect transistors. Single nanowires were aligned perpendicular to underlying bottom gates using a resist-trench alignment technique. Top gates were then defined aligned to the bottom gates to form gate-all-around structures. This approach overcomes significant limitations in minimal obtainable gate length and gate-length control in previous horizontal wrap-gated nanowire transistors that arise because the gate is defined by wet-etching. In the method presented here gate-length control is limited by the resolution of the electron-beam-lithography process. We demonstrate the versatility of our approach by fabricating a device with an independent bottom gate, top gate, and gate-all-around structure as well as a device with three independent gate-all-around structures with 300, 200, and 150 nm gate length. Our method enables us to achieve subthreshold swings as low as 38 mV dec-1 at 77 K for a 150 nm gate length.

p-GaAs Nanowire Metal-Semiconductor Field-Effect Transistors with Near-Thermal Limit Gating.

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical subthreshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio ∼105, on-resistance ∼700 kΩ, contact resistance ∼30 kΩ, peak transconductance 1.2 µS/µm, and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates while leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance.

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors.

We report the development of nanowire field-effect transistors featuring an ultrathin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally coated nanowires, which we used to produce functional Ω-gate and gate-all-around structures. These give subthreshold swings as low as 140 mV/dec and on/off ratios exceeding 103 at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically treated nanowire surfaces, a feature generally not possible with oxides produced by atomic layer deposition due to the surface "self-cleaning" effect. Our results highlight the potential for parylene as an alternative ultrathin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

Towards low-dimensional hole systems in Be-doped GaAs nanowires.

GaAs was central to the development of quantum devices but is rarely used for nanowire-based quantum devices with InAs, InSb and SiGe instead taking the leading role. p-type GaAs nanowires offer a path to studying strongly confined 0D and 1D hole systems with strong spin-orbit effects, motivating our development of nanowire transistors featuring Be-doped p-type GaAs nanowires, AuBe alloy contacts and patterned local gate electrodes towards making nanowire-based quantum hole devices. We report on nanowire transistors with traditional substrate back-gates and EBL-defined metal/oxide top-gates produced using GaAs nanowires with three different Be-doping densities and various AuBe contact processing recipes. We show that contact annealing only brings small improvements for the moderately doped devices under conditions of lower anneal temperature and short anneal time. We only obtain good transistor performance for moderate doping, with conduction freezing out at low temperature for lowly doped nanowires and inability to reach a clear off-state under gating for the highly doped nanowires. Our best devices give on-state conductivity 95 nS, off-state conductivity 2 pS, on-off ratio [Formula: see text], and sub-threshold slope 50 mV/dec at [Formula: see text] K. Lastly, we made a device featuring a moderately doped nanowire with annealed contacts and multiple top-gates. Top-gate sweeps show a plateau in the sub-threshold region that is reproducible in separate cool-downs and indicative of possible conductance quantisation highlighting the potential for future quantum device studies in this material system.

InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments.

We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favorable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.

Fully tunable, non-invasive thermal biasing of gated nanostructures suitable for low-temperature studies.

There is much recent interest in the thermoelectric (TE) characterization of single nanostructures at low temperatures, because such measurements yield information that is complementary to traditional conductance measurements, and because they may lead to novel paradigms for TE energy conversion. However, previously reported techniques for thermal biasing of nanostructures are difficult to use at low temperatures because of unintended global device heating, the lack of ability to continuously tune the thermal bias, or limited compatibility with gating techniques. By placing a heater directly on top of the electrical contact to a single InAs nanowire, we demonstrate fully tunable thermal biases of up to several tens of Kelvin, combined with negligible overall heating of the device, and with full functionality of a back gate, in the temperature range between 4 K and 300 K.