Implementation of Bayesian networks and Bayesian inference using a Cu0.1Te0.9/HfO2/Pt threshold switching memristor.

Bayesian networks and Bayesian inference, which forecast uncertain causal relationships within a stochastic framework, are used in various artificial intelligence applications. However, implementing hardware circuits for the Bayesian inference has shortcomings regarding device performance and circuit complexity. This work proposed a Bayesian network and inference circuit using a Cu0.1Te0.9/HfO2/Pt volatile memristor, a probabilistic bit neuron that can control the probability of being 'true' or 'false.' Nodal probabilities within the network are feasibly sampled with low errors, even with the device's cycle-to-cycle variations. Furthermore, Bayesian inference of all conditional probabilities within the network is implemented with low power (<186 nW) and energy consumption (441.4 fJ), and a normalized mean squared error of ∼7.5 × 10-4 through division feedback logic with a variational learning rate to suppress the inherent variation of the memristor. The suggested memristor-based Bayesian network shows the potential to replace the conventional complementary metal oxide semiconductor-based Bayesian estimation method with power efficiency using a stochastic computing method.

Vertically Stackable Ovonic Threshold Switch Oscillator Using Atomic Layer Deposited Ge0.6Se0.4 Film for High-Density Artificial Neural Networks.

Nanodevice oscillators (nano-oscillators) have received considerable attention to implement in neuromorphic computing as hardware because they can significantly improve the device integration density and energy efficiency compared to complementary metal oxide semiconductor circuit-based oscillators. This work demonstrates vertically stackable nano-oscillators using an ovonic threshold switch (OTS) for high-density neuromorphic hardware. A vertically stackable Ge0.6Se0.4 OTS-oscillator (VOTS-OSC) is fabricated with a vertical crossbar array structure by growing Ge0.6Se0.4 film conformally on a contact hole structure using atomic layer deposition. The VOTS-OSC can be vertically integrated onto peripheral circuits without causing thermal damage because the fabrication temperature is <400 °C. The fabricated device exhibits oscillation characteristics, which can serve as leaky integrate-and-fire neurons in spiking neural networks (SNNs) and coupled oscillators in oscillatory neural networks (ONNs). For practical applications, pattern recognition and vertex coloring are demonstrated with SNNs and ONNs, respectively, using semiempirical simulations. This structure increases the oscillator integration density significantly, enabling complex tasks with a large number of oscillators. Moreover, it can enhance the computational speed of neural networks due to its rapid switching speed.

Bio-Inspired Organic Synaptor with In Situ Ion-Doped Ultrathin Polyelectrolyte Containing Acetylcholine-Like Cation.

An ion-based synaptic transistor (synaptor) is designed to emulate a biological synapse using controlled ion movements. However, developing a solid-state electrolyte that can facilitate ion movement while achieving large-scale integration remains challenging. Here, a bio-inspired organic synaptor (BioSyn) with an in situ ion-doped polyelectrolyte (i-IDOPE) is demonstrated. At the molecular scale, a polyelectrolyte containing the tert-amine cation, inspired by the neurotransmitter acetylcholine is synthesized using initiated chemical vapor deposition (iCVD) with in situ doping, a one-step vapor-phase deposition used to fabricate solid-state electrolytes. This method results in an ultrathin, but highly uniform and conformal solid-state electrolyte layer compatible with large-scale integration, a form that is not previously attainable. At a synapse scale, synapse functionality is replicated, including short-term and long-term synaptic plasticity (STSP and LTSP), along with a transformation from STSP to LTSP regulated by pre-synaptic voltage spikes. On a system scale, a reflex in a peripheral nervous system is mimicked by mounting the BioSyns on various substrates such as rigid glass, flexible polyethylene naphthalate, and stretchable poly(styrene-ethylene-butylene-styrene) for a decentralized processing unit. Finally, a classification accuracy of 90.6% is achieved through semi-empirical simulations of MNIST pattern recognition, incorporating the measured LTSP characteristics from the BioSyns.

2Memristor-1Capacitor Integrated Temporal Kernel for High-Dimensional Data Mapping.

Compact but precise feature-extracting ability is core to processing complex computational tasks in neuromorphic hardware. Physical reservoir computing (RC) offers a robust framework to map temporal data into a high-dimensional space using the time dynamics of a material system, such as a volatile memristor. However, conventional physical RC systems have limited dynamics for the given material properties, restricting the methods to increase their dimensionality. This study proposes an integrated temporal kernel composed of a 2-memristor and 1-capacitor (2M1C) using a W/HfO2/TiN memristor and TiN/ZrO2/Al2O3/ZrO2/TiN capacitor to achieve higher dimensionality and tunable dynamics. The kernel elements are carefully designed and fabricated into an integrated array, of which performances are evaluated under diverse conditions. By optimizing the time dynamics of the 2M1C kernel, each memristor simultaneously extracts complementary information from input signals. The MNIST benchmark digit classification task achieves a high accuracy of 94.3% with a (196×10) single-layer network. Analog input mapping ability is tested with a Mackey-Glass time series prediction, and the system records a normalized root mean square error of 0.04 with a 20×1 readout network, the smallest readout network ever used for Mackey-Glass prediction in RC. These performances demonstrate its high potential for efficient temporal data analysis.

A Nanoscale Bistable Resistor for an Oscillatory Neural Network.

Coupled oscillators construct an oscillatory neural network (ONN) by mimicking the interactions among neurons in the human brain. This work demonstrates a fully CMOS-based oscillator consisting of a bistable resistor (biristor), which shares a structure identical with that of a metal-oxide-semiconductor field-effect transistor, except for the use of a gate electrode. The biristor-based oscillator (birillator) generates oscillating voltage signals in the form of spikes due to a single transistor latch phenomenon. When two birillators are connected with a coupling capacitor, they become synchronized with a phase difference of 180°. These coupled oscillation characteristics are experimentally investigated for an ONN. As practical applications of the ONN with coupled birillators, edge detection and vertex coloring are conducted by encoding information into phase differences between them. The proposed fully CMOS-based birillators are advantageous for low power consumption, high CMOS compatibility, and a compact footprint area.

A high-dimensional in-sensor reservoir computing system with optoelectronic memristors for high-performance neuromorphic machine vision.

In-sensor reservoir computing (RC) is a promising technology to reduce power consumption and training costs of machine vision systems by processing optical signals temporally. This study demonstrates a high-dimensional in-sensor RC system with optoelectronic memristors to enhance the performance of the in-sensor RC system. Because optoelectronic memristors can respond to both optical and electrical stimuli, optical and electrical masks are proposed to improve the dimensionality and performance of the in-sensor RC system. An optical mask is employed to regulate the wavelength of light, while an electrical mask is used to control the initial conductance of zinc oxide optoelectronic memristors. The distinct characteristics of these two masks contribute to the representation of various distinguishable reservoir states, making it possible to implement diverse reservoir configurations with minimal correlation and to increase the dimensionality of the in-sensor RC system. Using the high-dimensional in-sensor RC system, handwritten digits are successfully classified with an accuracy of 94.1%. Furthermore, human action pattern recognition is achieved with a high accuracy of 99.4%. These high accuracies are achieved with the use of a single-layer readout network, which can significantly reduce the network size and training costs.

Spatiotemporal Data Processing with Memristor Crossbar-Array-Based Graph Reservoir.

Memristor-based physical reservoir computing (RC) is a robust framework for processing complex spatiotemporal data parallelly. However, conventional memristor-based reservoirs cannot capture the spatial relationship between the time-varying inputs due to the specific mapping scheme assigning one input signal to one memristor conductance. Here, a physical "graph reservoir" is introduced using a metal cell at the diagonal-crossbar array (mCBA) with dynamic self-rectifying memristors. Input and inverted input signals are applied to the word and bit lines of the mCBA, respectively, storing the correlation information between input signals in the memristors. In this way, the mCBA graph reservoirs can map the spatiotemporal correlation of the input data in a high-dimensional feature space. The high-dimensional mapping characteristics of the graph reservoir achieve notable results, including a normalized root-mean-square error of 0.09 in Mackey-Glass time series prediction, a 97.21% accuracy in MNIST recognition, and an 80.0% diagnostic accuracy in human connectome classification.

Cross-Wired Memristive Crossbar Array for Effective Graph Data Analysis.

Graphs adequately represent the enormous interconnections among numerous entities in big data, incurring high computational costs in analyzing them with conventional hardware. Physical graph representation (PGR) is an approach that replicates the graph within a physical system, allowing for efficient analysis. This study introduces a cross-wired crossbar array (cwCBA), uniquely connecting diagonal and non-diagonal components in a CBA by a cross-wiring process. The cross-wired diagonal cells enable cwCBA to achieve precise PGR and dynamic node state control. For this purpose, a cwCBA is fabricated using Pt/Ta2O5/HfO2/TiN (PTHT) memristor with high on/off and self-rectifying characteristics. The structural and device benefits of PTHT cwCBA for enhanced PGR precision are highlighted, and the practical efficacy is demonstrated for two applications. First, it executes a dynamic path-finding algorithm, identifying the shortest paths in a dynamic graph. PTHT cwCBA shows a more accurate inferred distance and ≈1/3800 lower processing complexity than the conventional method. Second, it analyzes the protein-protein interaction (PPI) networks containing self-interacting proteins, which possess intricate characteristics compared to typical graphs. The PPI prediction results exhibit an average of 30.5% and 21.3% improvement in area under the curve and F1-score, respectively, compared to existing algorithms.

Vertically Integrated CMOS Ternary Logic Device with Low Static Power Consumption and High Packing Density.

A ternary logic system to realize the simplest multivalued logic architecture can enhance energy efficiency compared to a binary logic system by reducing the number of transistors and interconnections. For the ternary logic system, a ternary logic device to harness three stable states is needed. In this study, a vertically integrated complementary metal-oxide-semiconductor ternary logic device is demonstrated by monolithically integrating a thin-film transistor (TFT) over a transistor-based threshold switch (TTS). Because the TFT and the TTS have their own source (S), drain (D), and gate (G), there are physically six electrodes. But the hybrid ternary logic device of the TFT over the TTS has only four electrodes: S, D, GTFT, and GTTS like a single MOSFET. It is because the D of the underlying TTS is electrically tied with the S of the superjacent TFT. By combining an on- and off-state of the TFT and the TTS, ternary logic values of low current ("0"-state), middle current ("1"-state), and high current ("2"-state) are realized. Particularly, static power consumption at the "1"-state is decreased by employing the TTS with low off-state leakage current compared to previously reported other ternary logic devices. In addition, a footprint of the ternary logic device with the vertically overlaying structure that has a framework of "one over the other" can be lowered by roughly twice compared to that with the laterally deployed structure that has an organization of "one alongside the other".

3D Neuromorphic Hardware with Single Thin-Film Transistor Synapses Over Single Thin-Body Transistor Neurons by Monolithic Vertical Integration.

Neuromorphic hardware with a spiking neural network (SNN) can significantly enhance the energy efficiency for artificial intelligence (AI) functions owing to its event-driven and spatiotemporally sparse operations. However, an artificial neuron and synapse based on complex complementary metal-oxide-semiconductor (CMOS) circuits limit the scalability and energy efficiency of neuromorphic hardware. In this work, a neuromorphic module is demonstrated composed of synapses over neurons realized by monolithic vertical integration. The synapse at top is a single thin-film transistor (1TFT-synapse) made of poly-crystalline silicon film and the neuron at bottom is another single transistor (1T-neuron) made of single-crystalline silicon. Excimer laser annealing (ELA) is applied to activate dopants for the 1TFT-synapse at the top and rapid thermal annealing (RTA) is applied to do so for the 1T-neuron at the bottom. Internal electro-thermal annealing (ETA) via the generation of Joule heat is also used to enhance the endurance of the 1TFT-synapse without transferring heat to the 1T-neuron at the bottom. As neuromorphic vision sensing, classification of American Sign Language (ASL) is conducted with the fabricated neuromorphic module. Its classification accuracy on ASL is ≈92.3% even after 204 800 update pulses.

Leaky FinFET for Reservoir Computing with Temporal Signal Processing.

Reservoir computing can greatly reduce the hardware and training costs of recurrent neural networks with temporal data processing. To implement reservoir computing in a hardware form, physical reservoirs transforming sequential inputs into a high-dimensional feature space are necessary. In this work, a physical reservoir with a leaky fin-shaped field-effect transistor (L-FinFET) is demonstrated by the positive use of a short-term memory property arising from the absence of an energy barrier to suppress the tunneling current. Nevertheless, the L-FinFET reservoir does not lose its multiple memory states. The L-FinFET reservoir consumes very low power when encoding temporal inputs because the gate serves as an enabler of the write operation, even in the off-state, due to its physical insulation from the channel. In addition, the small footprint area arising from the scalability of the FinFET due to its multiple-gate structure is advantageous for reducing the chip size. After the experimental proof of 4-bit reservoir operations with 16 states for temporal signal processing, handwritten digits in the Modified National Institute of Standards and Technology dataset are classified by reservoir computing.

Artificial Multisensory Neuron with a Single Transistor for Multimodal Perception through Hybrid Visual and Thermal Sensing.

An artificial multisensory device applicable to in-sensor computing is demonstrated with a single-transistor neuron (1T-neuron) for multimodal perception. It simultaneously receives two sensing signals from visual and thermal stimuli. The 1T-neuron transforms these signals into electrical signals in the form of spiking and then fires them for a spiking neural network at the same time. This feature makes it feasible to realize input neurons for multimodal sensing. Visual and thermal sensing is achieved due to the inherent optical and thermal behaviors of the 1T-neuron. To demonstrate a neuromorphic multimodal sensing system with the artificial multisensory 1T-neuron, fingerprint recognition, widely used for biometric security, is implemented. Owing to the simultaneous sensing of heat as well as light, the proposed fingerprint recognition system composed of multisensory 1T-neurons not only identifies a genuine pattern but also judges whether or not it is forged.

Synaptic Segmented Transistor with Improved Linearity by Schottky Junctions and Accelerated Speed by Double-Layered Nitride.

Neuromorphic devices have been extensively studied to overcome the limitations of a von Neumann system for artificial intelligence. A synaptic device is one of the most important components in the hardware integration for a neuromorphic system because a number of synaptic devices can be connected to a neuron with compactness as high as possible. Therefore, synaptic devices using silicon-based memory, which are advantageous for a high packing density and mass production due to matured fabrication technologies, have attracted considerable attention. In this study, a segmented transistor devoted to an artificial synapse is proposed for the first time to improve the linearity of the potentiation and depression (P/D). It is a complementary metal oxide semiconductor (CMOS)-compatible device that harnesses both non-ohmic Schottky junctions of the source and drain for improved weight linearity and double-layered nitride for enhanced speed. It shows three distinct and unique segments in drain current-gate voltage transfer characteristics induced by Schottky junctions. In addition, the different stoichiometries of SixNy for a double-layered nitride is utilized as a charge trap layer for boosting the operation speed. This work can bring the industry potentially one step closer to realizing the mass production of hardware-based synaptic devices in the future.

A Bioinspired Artificial Gustatory Neuron for a Neuromorphic Based Electronic Tongue.

A novel biomimicked neuromorphic sensor for an energy efficient and highly scalable electronic tongue (E-tongue) is demonstrated with a metal-oxide-semiconductor field-effect transistor (MOSFET). By mimicking a biological gustatory neuron, the proposed E-tongue can simultaneously detect ion concentrations of chemicals on an extended gate and encode spike signals on the MOSFET, which acts as an input neuron in a spiking neural network (SNN). Such in-sensor neuromorphic functioning can reduce the energy and area consumption of the conventional E-tongue hardware. pH-sensitive and sodium-sensitive artificial gustatory neurons are implemented by using two different sensing materials: Al2O3 for pH sensing and sodium ionophore X for sodium ion sensing. In addition, a sensitivity control function inspired by the biological sensory neuron is demonstrated. After the unit device characterization of the artificial gustatory neuron, a fully hardware-based E-tongue that can classify two distinct liquids is demonstrated to show a practical application of the artificial gustatory neurons.

Artificial Olfactory Neuron for an In-Sensor Neuromorphic Nose.

A neuromorphic module of an electronic nose (E-nose) is demonstrated by hybridizing a chemoresistive gas sensor made of a semiconductor metal oxide (SMO) and a single transistor neuron (1T-neuron) made of a metal-oxide-semiconductor field-effect transistor (MOSFET). By mimicking a biological olfactory neuron, it simultaneously detects a gas and encoded spike signals for in-sensor neuromorphic functioning. It identifies an odor source by analyzing the complicated mixed signals using a spiking neural network (SNN). The proposed E-nose does not require conversion circuits, which are essential for processing the sensory signals between the sensor array and processors in the conventional bulky E-nose. In addition, they do not have to include a central processing unit (CPU) and memory, which are required for von Neumann computing. The spike transmission of the biological olfactory system, which is known to be the main factor for reducing power consumption, is realized with the SNN for power savings compared to the conventional E-nose with a deep neural network (DNN). Therefore, the proposed neuromorphic E-nose is promising for application to Internet of Things (IoT), which demands a highly scalable and energy-efficient system. As a practical example, it is employed as an electronic sommelier by classifying different types of wines.

Mnemonic-opto-synaptic transistor for in-sensor vision system.

A mnemonic-opto-synaptic transistor (MOST) that has triple functions is demonstrated for an in-sensor vision system. It memorizes a photoresponsivity that corresponds to a synaptic weight as a memory cell, senses light as a photodetector, and performs weight updates as a synapse for machine vision with an artificial neural network (ANN). Herein the memory function added to a previous photodetecting device combined with a photodetector and a synapse provides a technical breakthrough for realizing in-sensor processing that is able to perform image sensing and signal processing in a sensor. A charge trap layer (CTL) was intercalated to gate dielectrics of a vertical pillar-shaped transistor for the memory function. Weight memorized in the CTL makes photoresponsivity tunable for real-time multiplication of the image with a memorized photoresponsivity matrix. Therefore, these multi-faceted features can allow in-sensor processing without external memory for the in-sensor vision system. In particular, the in-sensor vision system can enhance speed and energy efficiency compared to a conventional vision system due to the simultaneous preprocessing of massive data at sensor nodes prior to ANN nodes. Recognition of a simple pattern was demonstrated with full sets of the fabricated MOSTs. Furthermore, recognition of complex hand-written digits in the MNIST database was also demonstrated with software simulations.

Self-Powered Artificial Mechanoreceptor Based on Triboelectrification for a Neuromorphic Tactile System.

A self-powered artificial mechanoreceptor module is demonstrated with a triboelectric nanogenerator (TENG) as a pressure sensor with sustainable energy harvesting and a biristor as a neuron. By mimicking a biological mechanoreceptor, it simultaneously detects the pressure and encodes spike signals to act as an input neuron of a spiking neural network (SNN). A self-powered neuromorphic tactile system composed of artificial mechanoreceptor modules with an energy harvester can greatly reduce the power consumption compared to the conventional tactile system based on von Neumann computing, as the artificial mechanoreceptor module itself does not demand an external energy source and information is transmitted with spikes in a SNN. In addition, the system can detect low pressures near 3 kPa due to the high output range of the TENG. It therefore can be advantageously applied to robotics, prosthetics, and medical and healthcare devices, which demand low energy consumption and low-pressure detection levels. For practical applications of the neuromorphic tactile system, classification of handwritten digits is demonstrated with a software-based simulation. Furthermore, a fully hardware-based breath-monitoring system is implemented using artificial mechanoreceptor modules capable of detecting wind pressure of exhalation in the case of pulmonary respiration and bending pressure in the case of abdominal breathing.

Ultra-fast data sanitization of SRAM by back-biasing to resist a cold boot attack.

Although SRAM is a well-established type of volatile memory, data remanence has been observed at low temperature even for a power-off state, and thus it is vulnerable to a physical cold boot attack. To address this, an ultra-fast data sanitization method within 5 ns is demonstrated with physics-based simulations for avoidance of the cold boot attack to SRAM. Back-bias, which can control device parameters of CMOS, such as threshold voltage and leakage current, was utilized for the ultra-fast data sanitization. It is applicable to temporary erasing with data recoverability against a low-level attack as well as permanent erasing with data irrecoverability against a high-level attack.

A Vertical Silicon Nanowire Based Single Transistor Neuron with Excitatory, Inhibitory, and Myelination Functions for Highly Scalable Neuromorphic Hardware.

A single transistor neuron (1T-neuron) is demonstrated by using a vertically protruded nanowire from an 8 in. silicon (Si) wafer. The 1T-neuron adopts a gate-all-around structure to completely surround the Si nanowire (Si-NW) to make a floating body and allow aggressive downscaling. The Si-NW is composed of an n+ drain at the top, n+ source at the bottom, and p-type floating body at the middle, which are self-aligned vertically. Thus, it occupies a small footprint area. The gate controls an excitatory/inhibitory function. In addition, myelination of a biological neuron that changes membrane capacitance is mimicked by an inherently asymmetric source/drain structure. Two spiking frequencies at the same input current are controlled by whether the neuron is myelinated or unmyelinated. Using the vertical 1T-neuron, pattern recognition is demonstrated with both measurements and semiempirical circuit simulations. Furthermore, handwritten numbers in the MNIST database are recognized with accuracy of 93% by software-based simulations. Applicability of the vertical 1T-neuron to various neural networks is verified, including a single-layer perceptron, multilayer perceptron, and spiking neural network.