Optimization of GOPS-Based Functionalization Process and Impact of Aptamer Grafting on the Si Nanonet FET Electrical Properties as First Steps towards Thrombin Electrical Detection.

Field effect transistors (FETs) based on networks of randomly oriented Si nanowires (Si nanonets or Si NNs) were biomodified using Thrombin Binding Aptamer (TBA-15) probe with the final objective to sense thrombin by electrical detection. In this work, the impact of the biomodification on the electrical properties of the Si NN-FETs was studied. First, the results that were obtained for the optimization of the (3-Glycidyloxypropyl)trimethoxysilane (GOPS)-based biofunctionalization process by using UV radiation are reported. The biofunctionalized devices were analyzed by atomic force microscopy (AFM) and scanning transmission electron microscopy (STEM), proving that TBA-15 probes were properly grafted on the surface of the devices, and by means of epifluorescence microscopy it was possible to demonstrate that the UV-assisted GOPS-based functionalization notably improves the homogeneity of the surface DNA distribution. Later, the electrical characteristics of 80 devices were analyzed before and after the biofunctionalization process, indicating that the results are highly dependent on the experimental protocol. We found that the TBA-15 hybridization capacity with its complementary strand is time dependent and that the transfer characteristics of the Si NN-FETs obtained after the TBA-15 probe grafting are also time dependent. These results help to elucidate and define the experimental precautions that must be taken into account to fabricate reproducible devices.

Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application.

Silicon ribbons (SiRi) have been well-established as highly sensitive transducers for biosensing applications thanks to their high surface to volume ratio. However, selective and multiplexed detection of biomarkers remains a challenge. Further, very few attempts have been made to integrate SiRi with complementary-metal-oxide-semiconductor (CMOS) circuits to form a complete lab-on-chip (LOC). Integration of SiRi with CMOS will facilitate real time detection of the output signal and provide a compact small sized LOC. Here, we propose a novel pixel based SiRi device monolithically integrated with CMOS field-effect-transistors (FET) for real-time selective multiplexed detection. The SiRi pixels are fabricated on a silicon-on-insulator wafer using a top-down method. Each pixel houses a control FET, fluid-gate (FG) and SiRi sensor. The pixel is controlled by simultaneously applying frontgate (VG) and backgate voltage (VBG). The liquid potential can be monitored using the FG. We report the transfer characteristics (ID-VG) of N- and P-type SiRi pixels. Further, the ID-VG characteristics of the SiRis are studied at different VBG. The application of VBG to turn ON the SiRi modulates the subthreshold slope (SS) and threshold voltage (VTH) of the control FET. Particularly, N-type pixels cannot be turned OFF due to the control NFET operating in the strong inversion regime. This is due to large VBG (≥25 V) application to turn ON the SiRi sensor. Conversely, the P-type SiRi sensors do not require large VBG to switch ON. Thus, P-type pixels exhibit excellent ION/IOFF ≥ 106, SS of 70⁻80 mV/dec and VTH of 0.5 V. These promising results will empower the large-scale cost-efficient production of SiRi based LOC sensors.

Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks.

The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed La x Ge y O z interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (1 0 0) Ge down to 3 × 1011 eV-1 cm-2 are demonstrated. The formation of the high-k La x Ge y O z layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.