Polymer waveguides for electro-optical integration in data centers and high-performance computers.

To satisfy the intra- and inter-system bandwidth requirements of future data centers and high-performance computers, low-cost low-power high-throughput optical interconnects will become a key enabling technology. To tightly integrate optics with the computing hardware, particularly in the context of CMOS-compatible silicon photonics, optical printed circuit boards using polymer waveguides are considered as a formidable platform. IBM Research has already demonstrated the essential silicon photonics and interconnection building blocks. A remaining challenge is electro-optical packaging, i.e., the connection of the silicon photonics chips with the system. In this paper, we present a new single-mode polymer waveguide technology and a scalable method for building the optical interface between silicon photonics chips and single-mode polymer waveguides.

Slotted photonic crystal nanobeam cavity with an ultrahigh quality factor-to-mode volume ratio.

We describe the design, fabrication, and characterization of a 1-dimensional silicon photonic crystal cavity with a quality factor-to-mode volume ratio greater than 10(7), which exceeds the highest previous values by an order of magnitude. The maximum of the electric field is outside the silicon in a void formed by a central slot. An extremely small calculated mode volume of 0.0096 (λvac/n)(3) is achieved through the abrupt change of the electric field in the slot, despite which a high quality factor of 8.2 × 10(5) is predicted by simulation. Quality factors up to 1.4 × 10(5) are measured in actual devices. The observation of pronounced thermo-optic bistability is consistent with the strong confinement of light in these cavities.

A single InP-on-SOI microdisk for high-speed half-duplex on-chip optical links.

We demonstrate for the first time that a single compact, electrically contacted indium phosphide based microdisk heterogeneously integrated on a silicon-on-insulator waveguide can be used as both a high-speed modulator and photo detector. We demonstrate high-speed operation up to 10 Gb/s and present bit-error rate results of both operation modes.

A low-power high-speed InP microdisk modulator heterogeneously integrated on a SOI waveguide.

We report on the modulation characteristics of indium phosphide (InP) based microdisks heterogeneously integrated on a silicon-on-insulator (SOI) waveguide. We present static extinction ratios and dynamic operation up to 10 Gb/s. Operation with a bit-error rate below 1 × 10(-9) is demonstrated at 2.5, 5.0 and 10.0 Gb/s and the performance is compared with that of a commercial modulator. Power penalties are analyzed with respect to the pattern length. The power consumption is calculated and compared with state-of-the-art integrated modulator concepts. We demonstrate that InP microdisk modulators combine low-power and low-voltage operation with low footprint and high-speed. Moreover, the devices can be fabricated using the same technology as for lasers, detectors and wavelength converters, making them very attractive for co-integration.

Synthesis of graphene on silicon dioxide by a solid carbon source.

We report on a method for the fabrication of graphene on a silicon dioxide substrate by solid-state dissolution of an overlying stack of a silicon carbide and a nickel thin film. The carbon dissolves in the nickel by rapid thermal annealing. Upon cooling, the carbon segregates to the nickel surface forming a graphene layer over the entire nickel surface. By wet etching of the nickel layer, the graphene layer was allowed to settle on the original substrate. Scanning tunneling microscopy (STM) as well as Raman spectroscopy has been performed for characterization of the layers. Further insight into the morphology of the layers has been gained by Raman mapping indicating micrometer-size graphene grains. Devices for electrical measurement have been manufactured exhibiting a modulation of the transfer current by backgate electric fields. The presented approach allows for mass fabrication of polycrystalline graphene without transfer steps while using only CMOS compatible process steps.