9.4% efficient amorphous silicon solar cell on high aspect-ratio glass microcones.

High aspect-ratio three-dimensional (3D) a-Si:H solar cells have been fabricated to enhance a light absorption path while maintaining a short carrier collection length. Substantial efficiency enhancement in 3D solar cells was achieved due to the boost in JSC with no degradation of FF which is comparable to FF obtained from 2D solar cells.

Engineering of contact resistance between transparent single-walled carbon nanotube films and a-Si:H single junction solar cells by gold nanodots.

The viability of single-walled carbon nanotubes (SWCNTs) as a transparent conducting electrode on a-Si:H based single junction solar cells was explored. A Schottky barrier formed at a SWCNT/a-Si:H interface was removed by introducing high work function gold nanodots at the SWCNT/a-Si:H interface. This allows comparable device performance from SWCNT-electrode-based a-Si:H solar cells to that obtained by using conventional transparent conducting oxides.

Three-dimensional a-Si:H solar cells on glass nanocone arrays patterned by self-assembled Sn nanospheres.

We introduce a cost-effective method of forming size-tunable arrays of nanocones to act as a three-dimensional (3D) substrate for hydrogenated amorphous silicon (a-Si:H) solar cells. The method is based on self-assembled tin nanospheres with sizes in the range of 20 nm to 1.2 µm. By depositing these spheres on glass substrates and using them as an etch mask, we demonstrate the formation of glass nanopillars or nanocones, depending on process conditions. After deposition of 150 nm thick a-Si:H solar cell p-i-n stacks on the glass nanocones, we show an output efficiency of 7.6% with a record fill factor of ~69% for a nanopillar-based 3D solar cell. This represents up to 40% enhanced efficiency compared to planar solar cells and, to the best of our knowledge, is the first demonstration of nanostructured p-i-n a-Si:H solar cells on glass that is textured without optical lithography patterning methods.

Graphene flash memory.

Graphene's single atomic layer of sp(2) carbon has recently garnered much attention for its potential use in electronic applications. Here, we report a memory application for graphene, which we call graphene flash memory (GFM). GFM has the potential to exceed the performance of current flash memory technology by utilizing the intrinsic properties of graphene, such as high density of states, high work function, and low dimensionality. To this end, we have grown large-area graphene sheets by chemical vapor deposition and integrated them into a floating gate structure. GFM displays a wide memory window of ∼6 V at significantly low program/erase voltages of ±7 V. GFM also shows a long retention time of more than 10 years at room temperature. Additionally, simulations suggest that GFM suffers very little from cell-to-cell interference, potentially enabling scaling down far beyond current state-of-the-art flash memory devices.

A stacked memory device on logic 3D technology for ultra-high-density data storage.

We have demonstrated, for the first time, a novel three-dimensional (3D) memory chip architecture of stacked-memory-devices-on-logic (SMOL) achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. In order to realize the SMOL, a unique 3D Flash memory device and vertical integration structure have been successfully developed. The SMOL architecture has great potential to achieve tera-bit level memory density by stacking memory devices vertically and maximizing cell-area efficiency. Furthermore, various emerging devices could replace the 3D memory device to develop new 3D chip architectures.

Single-crystalline Ni2Ge/Ge/Ni2Ge nanowire heterostructure transistors.

In this study, we report on the formation of a single-crystalline Ni(2)Ge/Ge/Ni(2)Ge nanowire heterostructure and its field effect characteristics by controlled reaction between a supercritical fluid-liquid-solid (SFLS) synthesized Ge nanowire and Ni metal contacts. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) studies reveal a wide temperature range to convert the Ge nanowire to single-crystalline Ni(2)Ge by a thermal diffusion process. The maximum current density of the fully germanide Ni(2)Ge nanowires exceeds 3.5 × 10(7) A cm(-2), and the resistivity is about 88 µΩ cm. The in situ reaction examined by TEM shows atomically sharp interfaces for the Ni(2)Ge/Ge/Ni(2)Ge heterostructure. The interface epitaxial relationships are determined to be [Formula: see text] and [Formula: see text]. Back-gate field effect transistors (FETs) were also fabricated using this low resistivity Ni(2)Ge as source/drain contacts. Electrical measurements show a good p-type FET behavior with an on/off ratio over 10(3) and a one order of magnitude improvement in hole mobility from that of SFLS-synthesized Ge nanowire.

Electric-field-controlled ferromagnetism in high-Curie-temperature Mn0.05Ge0.95 quantum dots.

Electric-field manipulation of ferromagnetism has the potential for developing a new generation of electric devices to resolve the power consumption and variability issues in today's microelectronics industry. Among various dilute magnetic semiconductors (DMSs), group IV elements such as Si and Ge are the ideal material candidates because of their excellent compatibility with the conventional complementary metal-oxide-semiconductor (MOS) technology. Here we report, for the first time, the successful synthesis of self-assembled dilute magnetic Mn(0.05)Ge(0.95) quantum dots with ferromagnetic order above room temperature, and the demonstration of electric-field control of ferromagnetism in MOS ferromagnetic capacitors up to 100 K. We found that by applying electric fields to a MOS gate structure, the ferromagnetism of the channel layer can be effectively modulated through the change of hole concentration inside the quantum dots. Our results are fundamentally important in the understanding and to the realization of high-efficiency Ge-based spin field-effect transistors.

Metal nanodot memory by self-assembled block copolymer lift-off.

As information technology demands for larger capability in data storage continue, ultrahigh bit density memory devices have been extensively investigated. To produce an ultrahigh bit density memory device, multilevel cell operations that require several states in one cell have been proposed as one solution, which can also alleviate the scaling issues in the current state-of-the-art complementary metal oxide semiconductor technology. Here, we report the first demonstration of metal nanodot memory using a self-assembled block copolymer lift-off. This metal nanodot memory with simple low temperature processes produced an ultrawide memory window of 15 V at the +/-18 V voltage sweep. Such a large window can be adopted for multilevel cell operations. Scanning electron microscopy and transmission electron microscopy studies showed a periodic metal nanodot array with uniform distribution defined by the block copolymer pattern. Consequently, this metal nanodot memory has high potential to reduce the variability issues that metal nanocrystal memories previously had and multilevel cells with ultrawide memory windows can be fabricated with high reliability and manufacturability.