Tetracosanoic acids produced by 3-ketoacyl-CoA synthase 17 are required for synthesizing seed coat suberin in Arabidopsis.

Very long-chain fatty acids (VLCFAs) are precursors for the synthesis of membrane lipids, cuticular waxes, suberins, and storage oils in plants. 3-Ketoacyl CoA synthase (KCS) catalyzes the condensation of C2 units from malonyl-CoA to acyl-CoA, the first rate-limiting step in VLCFA synthesis. In this study, we revealed that Arabidopsis KCS17 catalyzes the elongation of C22-C24 VLCFAs required for synthesizing seed coat suberin. Histochemical analysis of Arabidopsis plants expressing GUS (ß-glucuronidase) under the control of the KCS17 promoter revealed predominant GUS expression in seed coats, petals, stigma, and developing pollen. The expression of KCS17:eYFP (enhanced yellow fluorescent protein) driven by the KCS17 promoter was observed in the outer integument1 of Arabidopsis seed coats. The KCS17:eYFP signal was detected in the endoplasmic reticulum of tobacco epidermal cells. The levels of C22 VLCFAs and their derivatives, primary alcohols, α,ω-alkane diols, ω-hydroxy fatty acids, and α,ω-dicarboxylic acids increased by ~2-fold, but those of C24 VLCFAs, ω-hydroxy fatty acids, and α,ω-dicarboxylic acids were reduced by half in kcs17-1 and kcs17-2 seed coats relative to the wild type (WT). The seed coat of kcs17 displayed decreased autofluorescence under UV and increased permeability to tetrazolium salt compared with the WT. Seed germination and seedling establishment of kcs17 were more delayed by salt and osmotic stress treatments than the WT. KCS17 formed homo- and hetero-interactions with KCR1, PAS2, and ECR, but not with PAS1. Therefore, KCS17-mediated VLCFA synthesis is required for suberin layer formation in Arabidopsis seed coats.

First-principles study on multiferroicity in the Cr2Ge2Te6/In2Se3 heterostructure influenced by finite strains.

Multiferroic materials that have more than two ferroicities at the same time have long been regarded as one of the strongest candidates to achieve technological breakthroughs in many kinds of nanodevice applications. Various types of multiferroic materials have been discovered and devised to date; however, related studies have been conducted without identifying a complete winner because each has a decisive disadvantage. The recently discovered multiferroicity in the 2D Cr2Ge2Te6/In2Se3 van der Waals heterostructure represents an important opportunity to create a new turning point in multiferroic research. Through first-principles density functional theory calculations, we studied the preferential characteristics of the spin magnetic moment of 2D Cr2Ge2Te6 induced by the ferroelectric switching of the In2Se3 monolayer in the presence of the strains that inevitably exist in any kind of heterostructure. From the results, we found that the multiferroicity in the Cr2Ge2Te6/In2Se3 heterostructure reacts quite sensitively to the strain level, revealing the possibility of manipulating multiferroic properties in the structure.

The Parametric Study of Armchair Graphene Nanoribbon Field Effect Transistor by Non-Equilibrium Green's Function Method.

We have carried out a comprehensive parametric analysis on the potential performance of a graphene nanoribbon field effect transistor (GNRFET). We modeled the behavior of GNRFETs with nanometer width GNR channels to formulate a self-consistent, non-equilibrium Green's function (NEGF) scheme in conjunction with the Poisson equation and allow the GNRFET to operate as a switch. Based on the results, we propose a metric to compete with current silicon CMOS highperformance (HP) or low-power (LP) devices, explaining that this can vary widely depending on the GNRFET structure parameters.

First principles study of oxygen vacancy activation energy barrier in zirconia-based resistive memory.

Unlike experimental measurements that appeared to be quite large activation barriers, oxygen vacancies in zirconia-based resistive random access memory (ReRAM) are believed to migrate with a fairly low energy barrier, and this discrepancy has not been noticed nor seriously questioned up to date. In this paper, we work on this problem by means of first-principles calculations categorizing all the possible migration pathways by crystallographic directions. From the results, it is found that the low activation energy of oxygen vacancy that is expected from the switching characteristic of the device is originated from +2q charged oxygen vacancies in a nanometer-sized filament migrating into a particular crystallographic direction of monoclinic zirconia.

Tuning of ionic mobility to improve the resistive switching behavior of Zn-doped CeO2.

Correlation between the resistive switching characteristics of Au/Zn-doped CeO2/Au devices and ionic mobility of CeO2 altered by the dopant concentration were explored. It was found that the ionic mobility of CeO2 has a profound effect on the operating voltages of the devices. The magnitude of operating voltage was observed to decrease when the doping concentration of Zn was increased up to 14%. After further increasing the doping level to 24%, the device hardly exhibits any resistive switching. At a low doping concentration, only isolated Vo existed in the CeO2 lattice. At an intermediate doping concentration, the association between dopant and Vo formed (Zn, Vo)× defect clusters. Low number density of these defect clusters initially favored the formation of Vo filament and led to a reduction in operating voltage. As the size and number density of (Zn, Vo)× defect clusters increased at a higher doping concentration, the ionic conductivity was limited with the trapping of isolated Vo by these defect clusters, which resulted in the diminishing of resistive switching. This research work provides a strategy for tuning the mobility of Vo to modulate resistive switching characteristics for non-volatile memory applications.

The origin of the exceptionally low activation energy of oxygen vacancy in tantalum pentoxide based resistive memory.

It is well known that collective migrations of oxygen vacancies in oxide is the key principle of resistance change in oxide-based resistive memory (OxRAM). The practical usefulness of OxRAM mainly arises from the fact that these oxygen vacancy migrations take place at relatively low operating voltages. The activation energy of oxygen vacancy migration, which can be inferred from the operational voltage of an OxRAM, is much smaller compared to the experimentally measured activation energy of oxygen, and the underlying mechanism of the discrepancy has not been highlighted yet. We ask this fundamental question in this paper for tantalum oxide which is one of the most commonly employed oxides in OxRAMs and try the theoretical answer based on the first-principles calculations. From the results, it is proven that the exceptionally large mobility of oxygen vacancy expected by the switching model can be well explained by the exceptionally low activation barrier of positively charged oxygen vacancy within the two-dimensional substructure.

A study on mechanism of resistance distribution characteristics of oxide-based resistive memory.

Although oxide-based resistive switching memory (OxRAM) is one of the strong next-generation high capacity memory candidates, it has the critical disadvantage that deviations of resistance levels is too severe to be adopted as a high capacity memory device. More specifically, it is known that the larger on/off current ratios in multi-level operated OxRAMs, the greater deviation of resistance levels from the targeted values. However, despite the seriousness of the problem there has been no concrete theoretical study on the underlying mechanisms of the phenomenon. In this paper, we introduce a theoretical model that clearly explain the underlying mechanism of making such characteristics of programmed resistance levels in multi-level OxRAMs. From this model, we can understand why there is a proportional relationship between resistance level and its deviation, and why it has such a specific range of proportionality constant measured experimentally. And this understanding can certainly reveal the true limitations of OxRAMs's performance.

Theoretical investigation of performance of armchair graphene nanoribbon field effect transistors.

In this paper, we theoretically investigate the highest possible expected performance for graphene nanoribbon field effect transistors (GNRFETs) for a wide range of operation voltages and device structure parameters, such as the width of the graphene nanoribbon and gate length. We formulated a self-consistent, non-equilibrium Green's function method in conjunction with the Poisson equation and modeled the operation of nanometer sized GNRFETs, of which GNR channels have finite bandgaps so that the GNRFET can operate as a switch. We propose a metric for competing with the current silicon CMOS high performance or low power devices and explain that this can vary greatly depending on the GNRFET structure parameters.

Quantitative analysis of charge trapping and classification of sub-gap states in MoS2 TFT by pulse I-V method.

The threshold voltage instabilities and huge hysteresis of MoS2 thin film transistors (TFTs) have raised concerns about their practical applicability in next-generation switching devices. These behaviors are associated with charge trapping, which stems from tunneling to the adjacent trap site, interfacial redox reaction and interface and/or bulk trap states. In this report, we present quantitative analysis on the electron charge trapping mechanism of MoS2 TFT by fast pulse I-V method and the space charge limited current (SCLC) measurement. By adopting the fast pulse I-V method, we were able to obtain effective mobility. In addition, the origin of the trap states was identified by disassembling the sub-gap states into interface trap and bulk trap states by simple extraction analysis. These measurement methods and analyses enable not only quantitative extraction of various traps but also an understanding of the charge transport mechanism in MoS2 TFTs. The fast I-V data and SCLC data obtained under various measurement temperatures and ambient show that electron transport to neighboring trap sites by tunneling is the main charge trapping mechanism in thin-MoS2 TFTs. This implies that interfacial traps account for most of the total sub-gap states while the bulk trap contribution is negligible, at approximately 0.40% and 0.26% in air and vacuum ambient, respectively. Thus, control of the interface trap states is crucial to further improve the performance of devices with thin channels.

Effect of hydrogen on dynamic charge transport in amorphous oxide thin film transistors.

Hydrogen in zinc oxide based semiconductors functions as a donor or a defect de-activator depending on its concentration, greatly affecting the device characteristics of oxide thin-film transistors (TFTs). Thus, controlling the hydrogen concentration in oxide semiconductors is very important for achieving high mobility and minimizing device instability. In this study, we investigated the charge transport dynamics of the amorphous semiconductor InGaZnO at various hydrogen concentrations as a function of the deposition temperature of the gate insulator. To examine the nature of dynamic charge trapping, we employed short-pulse current-voltage and transient current-time measurements. Among various examined oxide devices, that with a high hydrogen concentration exhibits the best performance characteristics, such as high saturation mobility (10.9 cm(2) v(-1) s(-1)), low subthreshold slope (0.12 V/dec), and negligible hysteresis, which stem from low defect densities and negligible transient charge trapping. Our finding indicates that hydrogen atoms effectively passivate the defects in subgap states of the bulk semiconductor, minimizing the mobility degradation and threshold voltage instability. This study indicates that hydrogen plays a useful role in TFTs by improving the device performance and stability.

Pulse I-V characterization of a nano-crystalline oxide device with sub-gap density of states.

Understanding the charge trapping nature of nano-crystalline oxide semiconductor thin film transistors (TFTs) is one of the most important requirements for their successful application. In our investigation, we employed a fast-pulsed I-V technique for understanding the charge trapping phenomenon and for characterizing the intrinsic device performance of an amorphous/nano-crystalline indium-hafnium-zinc-oxide semiconductor TFT with varying density of states in the bulk. Because of the negligible transient charging effect with a very short pulse, the source-to-drain current obtained with the fast-pulsed I-V measurement was higher than that measured by the direct-current characterization method. This is because the fast-pulsed I-V technique provides a charge-trap free environment, suggesting that it is a representative device characterization methodology of TFTs. In addition, a pulsed source-to-drain current versus time plot was used to quantify the dynamic trapping behavior. We found that the charge trapping phenomenon in amorphous/nano-crystalline indium-hafnium-zinc-oxide TFTs is attributable to the charging/discharging of sub-gap density of states in the bulk and is dictated by multiple trap-to-trap processes.

III-V compound semiconductors for mass-produced nano-electronics: theoretical studies on mobility degradation by dislocation.

As silicon-based electronics approach the limit of scaling for increasing the performance and chip density, III-V compound semiconductors have started to attract significant attention owing to their high carrier mobility. However, the mobility benefits of III-V compounds are too easily accepted, ignoring a harmful effect of unavoidable threading dislocations that could fundamentally limit the applicability of these materials in nanometer-scale electronics. In this paper, we present a theoretical model that describes the degradation of carrier mobility by charged dislocations in quantum-confined III-V semiconductor metal oxide field effect transistors (MOSFETs). Based on the results, we conclude that in order for III-V compound MOSFETs to outperform silicon MOSFETs, Fermi level pinning in the channel should be eliminated for yielding carriers with high injection velocity.

Dislocation scatterings in p-type Si(1-x)Ge(x) under weak electric field.

We present a theoretical model which describes hole mobility degradation by charged dislocations in p-type Si(1-x)Ge(x). The complete analytical expression of the dislocation mobility is calculated from the momentum relaxation time of hole carriers under weak electric field. The obtained dislocation mobility shows a T(3/2)/λ relation and is proportional to the germanium density x. We also suggest a criterion for negating scatterings by dislocations in terms of the controllable parameters such as acceptor dopant density, dislocation density, temperature, and Ge density x, etc.

A plasma-treated chalcogenide switch device for stackable scalable 3D nanoscale memory.

Stackable select devices such as the oxide p-n junction diode and the Schottky diode (one-way switch) have been proposed for non-volatile unipolar resistive switching devices; however, bidirectional select devices (or two-way switch) need to be developed for bipolar resistive switching devices. Here we report on a fully stackable switching device that solves several problems including current density, temperature stability, cycling endurance and cycle distribution. We demonstrate that the threshold switching device based on As-Ge-Te-Si material significantly improves cycling endurance performance by reactive nitrogen deposition and nitrogen plasma hardening. Formation of the thin Si3N4 glass layer by the plasma treatment retards tellurium diffusion during cycling. Scalability of threshold switching devices is measured down to 30 nm scale with extremely fast switching speed of ~2 ns.

Modeling for multilevel switching in oxide-based bipolar resistive memory.

We report a physical model for multilevel switching in oxide-based bipolar resistive memory (ReRAM). To confirm the validity of the model, we conduct experiments with tantalum-oxide-based ReRAM of which multi-resistance levels are obtained by reset voltage modifications. It is also noticeable that, in addition to multilevel switching capability, the ReRAM exhibits extremely different switching timescales, i.e. of the order of 10(-7) s to 10(0) s, with regard to reset voltages of only a few volts difference which can be well explained by our model. It is demonstrated that with this simple model, multilevel switching behavior in oxide bipolar ReRAM can be described not only qualitatively but also quantitatively.

A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O(5-x)/TaO(2-x) bilayer structures.

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications.

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al2O3/SiO2) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.