Multi-scale simulations of two dimensional material based devices: the NanoTCAD ViDES suite.

NanoTCAD ViDES (Versatile DEvice Simulator) is an open-source suite of computing codes aimed at assessing the operation and the performance of nanoelectronic devices. It has served the computational nanoelectronic community for almost two decades and it is freely available to researchers around the world in its website (http://vides.nanotcad.com), being employed in hundreds of works by many electronic device simulation groups worldwide. We revise the code structure and its main modules and we present the new features directed towards (i) multi-scale approaches exploiting ab-initio electron-structure calculations, aiming at the exploitation of new physics in electronic devices, (ii) the inclusion of arbitrary heterostructures of layered materials to devise original device architectures and operation, and (iii) the exploration of novel low-cost, green technologies in the mesoscopic scale, as, e.g. printed electronics.

Rhombohedral-stacked bilayer transition metal dichalcogenides for high-performance atomically thin CMOS devices.

Van der Waals coupling with different stacking configurations is emerging as a powerful method to tune the optical and electronic properties of atomically thin two-dimensional materials. Here, we investigate 3R-stacked transition-metal dichalcogenides as a possible option for high-performance atomically thin field-effect transistors (FETs). We report that the effective mobility of 3R bilayer WS2 (WSe2) is 65% (50%) higher than that of 2H WS2 (WSe2). The 3R bilayer WS2 n-type FET exhibits a high on-state current of 480 µA/µm at Vds = 1 V and an ultralow on-state resistance of 1 kilohm·µm. Our observations, together with multiscale simulations, reveal that these improvements originate from the strong interlayer coupling in the 3R stacking, which is reflected in a higher conductance compared to the 2H stacking. Our method provides a general and scalable route toward advanced channel materials in future electronic devices for ultimate scaling, especially for complementary metal oxide semiconductor applications.

Substitutional p-Type Doping in NbS2 -MoS2 Lateral Heterostructures Grown by MOCVD.

Monolayer MoS2 has attracted significant attention owing to its excellent performance as an n-type semiconductor from the transition metal dichalcogenide (TMDC) family. It is however strongly desired to develop controllable synthesis methods for 2D p-type MoS2 , which is crucial for complementary logic applications but remains difficult. In this work, high-quality NbS2 -MoS2 lateral heterostructures are synthesized by one-step metal-organic chemical vapor deposition (MOCVD) together with monolayer MoS2 substitutionally doped by Nb, resulting in a p-type doped behavior. The heterojunction shows a p-type transfer characteristic with a high on/off current ratio of ≈104 , exceeding previously reported values. The band structure through the NbS2 -MoS2 heterojunction is investigated by density functional theory (DFT) and quantum transport simulations. This work provides a scalable approach to synthesize substitutionally doped TMDC materials and provides an insight into the interface between 2D metals and semiconductors in lateral heterostructures, which is imperative for the development of next-generation nanoelectronics and highly integrated devices.

A green approach to develop zeolite-thymol antimicrobial composites: analytical characterization and antimicrobial activity evaluation.

In this work, the development, analytical characterization and bioactivity of zeolite-thymol composites, obtained using wet, semi-dry and dry processes, were carried out in order to obtain sustainable and powerful antimicrobial additives. FT-IR, XRD, DSC, TGA, SEM and B.E.T. analyses were carried out to gain comprehensive information on the chemical-physical, thermal, and morphological features of the composites. GC-MS analyses allowed quantifying the active molecule loaded in the zeolite, released by the functionalized composites and its stability over time. Among the three procedures, the dry approach allowed to reach the highest thymol loading content and efficiency (49.8 ± 1.6% and 99.6 ± 1.2%, respectively), as well as the highest composite specific surface area value, feature which promises the best interaction between the surface of the composite and the bacterial population. Therefore, the bioactive surface of composites obtained by this solvent-free method was assayed for its antimicrobial activity against four microbial strains belonging to Staphylococcus aureus, Escherichia coli, Pseudomonas aeruginosa and Candida albicans species. The higher antimicrobial activity produced by the solvent-free composite in comparison with that of pure thymol, at the same thymol concentration, was ascribed to the large interfacial contact between the composite and the bacterial target. This feature, together with its enhanced storage stability, suggested that this composite could be employed as effective additives for the development of antimicrobial biointerfaces for food, home and personal care applications.

Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2.

Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electronics requires increased energy efficiency of processors for specialized data-driven applications. Here, we show how an in-memory processor fabricated using a two-dimensional materials platform can potentially outperform its silicon counterparts in both standard and nontraditional Von Neumann architectures for artificial neural networks. We have fabricated a flash memory array with a two-dimensional channel using wafer-scale MoS2. Simulations and experiments show that the device can be scaled down to sub-micrometer channel length without any significant impact on its memory performance and that in simulation a reasonable memory window still exists at sub-50 nm channel lengths. Each device conductance in our circuit can be tuned with a 4-bit precision by closed-loop programming. Using our physical circuit, we demonstrate seven-segment digit display classification with a 91.5% accuracy with training performed ex situ and transferred from a host. Further simulations project that at a system level, the large memory arrays can perform AlexNet classification with an upper limit of 50 000 TOpS/W, potentially outperforming neural network integrated circuits based on double-poly CMOS technology.

Physical insights on transistors based on lateral heterostructures of monolayer and multilayer PtSe2 via Ab initio modelling of interfaces.

Lateral heterostructures (LH) of monolayer-multilayer regions of the same noble transition metal dichalcogenide, such as platinum diselenide (PtSe2), are promising options for the fabrication of efficient two-dimensional field-effect transistors (FETs), by exploiting the dependence of the energy gap on the number of layers and the intrinsically high quality of the heterojunctions. Key for future progress in this direction is understanding the effects of the physics of the lateral interfaces on far-from-equilibrium transport properties. In this work, a multi-scale approach to device simulation, capable to include ab-initio modelling of the interfaces in a computationally efficient way, is presented. As an application, p- and n-type monolayer-multilayer PtSe2 LH-FETs are investigated, considering design parameters such as channel length, number of layers and junction quality. The simulations suggest that such transistors can provide high performance in terms of subthreshold characteristics and switching behavior, and that a single channel device is not capable, even in the ballistic defectless limit, to satisfy the requirements of the semiconductor roadmap for the next decade, and that stacked channel devices would be required. It is shown how ab-initio modelling of interfaces provides a reliable physical description of charge displacements in their proximity, which can be crucial to correctly predict device transport properties, especially in presence of strong dipoles, mixed stoichiometries or imperfections.

Low-voltage 2D materials-based printed field-effect transistors for integrated digital and analog electronics on paper.

Paper is the ideal substrate for the development of flexible and environmentally sustainable ubiquitous electronic systems, which, combined with two-dimensional materials, could be exploited in many Internet-of-Things applications, ranging from wearable electronics to smart packaging. Here we report high-performance MoS2 field-effect transistors on paper fabricated with a "channel array" approach, combining the advantages of two large-area techniques: chemical vapor deposition and inkjet-printing. The first allows the pre-deposition of a pattern of MoS2; the second, the printing of dielectric layers, contacts, and connections to complete transistors and circuits fabrication. Average ION/IOFF of 8 × 103 (up to 5 × 104) and mobility of 5.5 cm2 V-1 s-1 (up to 26 cm2 V-1 s-1) are obtained. Fully functional integrated circuits of digital and analog building blocks, such as logic gates and current mirrors, are demonstrated, highlighting the potential of this approach for ubiquitous electronics on paper.

Inkjet-printed graphene Hall mobility measurements and low-frequency noise characterization.

We report room temperature Hall mobility measurements, low temperature magnetoresistance analysis and low-frequency noise characterization of inkjet-printed graphene films on fused quartz and SiO2/Si substrates. We found that thermal annealing in vacuum at 450 °C is a necessary step in order to stabilize the Hall voltage across the devices, allowing their electrical characterization. The printed films present a minimum sheet resistance of 23.3 Ω sq-1 after annealing, and are n-type doped, with carrier concentrations in the low 1020 cm-3 range. The charge carrier mobility is found to increase with increasing film thickness, reaching a maximum value of 33 cm2 V-1 s-1 for a 480 nm-thick film printed on SiO2/Si. Low-frequency noise characterization shows a 1/f noise behavior and a Hooge parameter in the range of 0.1-1. These results represent the first in-depth electrical and noise characterization of transport in inkjet-printed graphene films, able to provide physical insights on the mechanisms at play.

Lateral Heterostructure Field-Effect Transistors Based on Two-Dimensional Material Stacks with Varying Thickness and Energy Filtering Source.

The bandgap dependence on the number of atomic layers of some families of two-dimensional (2D) materials can be exploited to engineer and use lateral heterostructures (LHs) as high-performance field-effect transistors (FETs). This option can provide very good lattice matching as well as high heterointerface quality. More importantly, this bandgap modulation with layer stacking can give rise to steep transitions in the density of states (DOS) of the 2D material that can eventually be used to achieve sub-60 mV/decade subthreshold swing in LH-FETs thanks to an energy-filtering source. We have observed this effect in the case of a PdS2 LH-FET due to the particular DOS of its bilayer configuration. Our results are based on ab initio and multiscale materials and device modeling and incite the exploration of the 2D-material design space in order to find more abrupt DOS transitions and better suitable candidates.

All-2D Material Inkjet-Printed Capacitors: Toward Fully Printed Integrated Circuits.

A well-defined insulating layer is of primary importance in the fabrication of passive ( e.g., capacitors) and active ( e.g., transistors) components in integrated circuits. One of the most widely known two-dimensional (2D) dielectric materials is hexagonal boron nitride (hBN). Solution-based techniques are cost-effective and allow simple methods to be used for device fabrication. In particular, inkjet printing is a low-cost, noncontact approach, which also allows for device design flexibility, produces no material wastage, and offers compatibility with almost any surface of interest, including flexible substrates. In this work, we use water-based and biocompatible graphene and hBN inks to fabricate all-2D material and inkjet-printed capacitors. We demonstrate an areal capacitance of 2.0 ± 0.3 nF cm-2 for a dielectric thickness of ∼3 µm and negligible leakage currents, averaged across more than 100 devices. This gives rise to a derived dielectric constant of 6.1 ± 1.7. The inkjet printed hBN dielectric has a breakdown field of 1.9 ± 0.3 MV cm-1. Fully printed capacitors with sub-micrometer hBN layer thicknesses have also been demonstrated. The capacitors are then exploited in two fully printed demonstrators: a resistor-capacitor (RC) low-pass filter and a graphene-based field effect transistor.

Publisher Correction: Quantum engineering of transistors based on 2D materials heterostructures.

In the version of this Perspective originally published, in the email address for the author Giuseppe Iannaccone, the surname was incorrectly given as "innaconne"; this has now been corrected in all versions of the Perspective. Also, an error in the production process led to Figs. 1, 2 and 3 being of low resolution; these have now been replaced with higher-quality versions.

Quantum engineering of transistors based on 2D materials heterostructures.

Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

Reconfigurable Diodes Based on Vertical WSe2 Transistors with van der Waals Bonded Contacts.

New device concepts can increase the functionality of scaled electronic devices, with reconfigurable diodes allowing the design of more compact logic gates being one of the examples. In recent years, there has been significant interest in creating reconfigurable diodes based on ultrathin transition metal dichalcogenide crystals due to their unique combination of gate-tunable charge carriers, high mobility, and sizeable band gap. Thanks to their large surface areas, these devices are constructed under planar geometry and the device characteristics are controlled by electrostatic gating through rather complex two independent local gates or ionic-liquid gating. In this work, similar reconfigurable diode action is demonstrated in a WSe2 transistor by only utilizing van der Waals bonded graphene and Co/h-BN contacts. Toward this, first the charge injection efficiencies into WSe2 by graphene and Co/h-BN contacts are characterized. While Co/h-BN contact results in nearly Schottky-barrier-free charge injection, graphene/WSe2 interface has an average barrier height of ≈80 meV. By taking the advantage of the electrostatic transparency of graphene and the different work-function values of graphene and Co/h-BN, vertical devices are constructed where different gate-tunable diode actions are demonstrated. This architecture reveals the opportunities for exploring new device concepts.

On current transients in MoS2 Field Effect Transistors.

We present an experimental investigation of slow transients in the gate and drain currents of MoS2-based transistors. We focus on the measurement of both the gate and drain currents and, from the comparative analysis of the current transients, we conclude that there are at least two independent trapping mechanisms: trapping of charges in the silicon oxide substrate, occurring with time constants of the order of tens of seconds and involving charge motion orthogonal to the MoS2 sheet, and trapping at the channel surface, which occurs with much longer time constants, in particular when the device is in a vacuum. We observe that the presence of such slow phenomena makes it very difficult to perform reliable low-frequency noise measurements, requiring a stable and repeatable steady-state bias point condition, and may explain the sometimes contradictory results that can be found in the literature about the dependence of the flicker noise power spectral density on gate bias.

High performance metal-insulator-graphene diodes for radio frequency power detection application.

Vertical metal-insulator-graphene (MIG) diodes for radio frequency (RF) power detection are realized using a scalable approach based on graphene grown by chemical vapor deposition and TiO2 as barrier material. The temperature dependent current flow through the diode can be described by thermionic emission theory taking into account a bias induced barrier lowering at the graphene TiO2 interface. The diodes show excellent figures of merit for static operation, including high on-current density of up to 28 A cm-2, high asymmetry of up to 520, strong maximum nonlinearity of up to 15, and large maximum responsivity of up to 26 V-1, outperforming state-of-the-art metal-insulator-metal and MIG diodes. RF power detection based on MIG diodes is demonstrated, showing a responsivity of 2.8 V W-1 at 2.4 GHz and 1.1 V W-1 at 49.4 GHz.

Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes.

Two-dimensional (2D) material based FETs are being considered for future technology nodes and high performance logic applications. However, a comprehensive assessment of 2D material based FETs has been lacking for high performance logic applications considering appropriate system level figure-of-merits (FOMs) e.g. delay, and energy-delay product. In this paper, we present guidelines for 2D material based FETs to meet sub-10 nm high performance logic requirements focusing on material requirement, device design, energy-delay optimization for the first time. We show the need for 2D materials with smaller effective mass in the transport direction and anisotropicity to meet the performance requirement for future technology nodes. We present novel device designs with one such 2D material (monolayer black-phosphorus) to keep Moore's alive for the HP logic in sub-5 nm gate length regime. With these device proposals we show that below 5 nm gate lengths 2D electrostatistics arising from gate stack design becomes more of a challenge than direct source-to-drain tunneling for 2D material-based FETs. Therefore, it is challenging to meet both delay and energy-delay requirement in sub-5 nm gate length regime without scaling both supply voltage (V DD ) and effective-oxide-thickness (EOT) below 0.5 V and 0.5 nm respectively.

Electrical properties of graphene-metal contacts.

The performance of devices and systems based on two-dimensional material systems depends critically on the quality of the contacts between 2D material and metal. A low contact resistance is an imperative requirement to consider graphene as a candidate material for electronic and optoelectronic devices. Unfortunately, measurements of contact resistance in the literature do not provide a consistent picture, due to limitations of current graphene technology, and to incomplete understanding of influencing factors. Here we show that the contact resistance is intrinsically dependent on graphene sheet resistance and on the chemistry of the graphene-metal interface. We present a physical model of the contacts based on ab-initio simulations and extensive experiments carried out on a large variety of samples with different graphene-metal contacts. Our model explains the spread in experimental results as due to uncontrolled graphene doping and suggests ways to engineer contact resistance. We also predict an achievable contact resistance of 30 Ω·µm for nickel electrodes, extremely promising for applications.

Temperature Compensation of Silicon Lamé Resonators Using Etch Holes: Theory and Design Methodology.

We present a new approach to the temperature compensation of MEMS Lamé resonators, based on the combined effect of the doping concentration and of the geometry of etch holes on the equivalent temperature coefficients of silicon. To this purpose, we develop and validate an analytical model which describes the effect of etch holes on the temperature stability of Lamé resonators through comparison with experiments available in the literature and finite-element method (FEM) simulations. We show that two interesting regions of the design space for Lamé resonators exist, where a cancellation of the first-order temperature coefficient of the resonance frequency is possible: [100]-oriented silicon with n-doping of 2.5 ·1019 cm -3 , and [110]-oriented silicon with p-doping higher than 1.4 ·1020 cm -3 .

Water-based and biocompatible 2D crystal inks for all-inkjet-printed heterostructures.

Exploiting the properties of two-dimensional crystals requires a mass production method able to produce heterostructures of arbitrary complexity on any substrate. Solution processing of graphene allows simple and low-cost techniques such as inkjet printing to be used for device fabrication. However, the available printable formulations are still far from ideal as they are either based on toxic solvents, have low concentration, or require time-consuming and expensive processing. In addition, none is suitable for thin-film heterostructure fabrication due to the re-mixing of different two-dimensional crystals leading to uncontrolled interfaces and poor device performance. Here, we show a general approach to achieve inkjet-printable, water-based, two-dimensional crystal formulations, which also provide optimal film formation for multi-stack fabrication. We show examples of all-inkjet-printed heterostructures, such as large-area arrays of photosensors on plastic and paper and programmable logic memory devices. Finally, in vitro dose-escalation cytotoxicity assays confirm the biocompatibility of the inks, extending their possible use to biomedical applications.

Performance of arsenene and antimonene double-gate MOSFETs from first principles.

In the race towards high-performance ultra-scaled devices, two-dimensional materials offer an alternative paradigm thanks to their atomic thickness suppressing short-channel effects. It is thus urgent to study the most promising candidates in realistic configurations, and here we present detailed multiscale simulations of field-effect transistors based on arsenene and antimonene monolayers as channels. The accuracy of first-principles approaches in describing electronic properties is combined with the efficiency of tight-binding Hamiltonians based on maximally localized Wannier functions to compute the transport properties of the devices. These simulations provide for the first time estimates on the upper limits for the electron and hole mobilities in the Takagi's approximation, including spin-orbit and multi-valley effects, and demonstrate that ultra-scaled devices in the sub-10-nm scale show a performance that is compliant with industry requirements.