Solution-Based Fabrication of Polycrystalline Si Thin-Film Transistors from Recycled Polysilanes.

Currently, research has been focusing on printing and laser crystallization of cyclosilanes, bringing to life polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with outstanding properties. However, the synthesis of these Si-based inks is generally complex and expensive. Here, we prove that a polysilane ink, obtained as a byproduct of silicon gases and derivatives, can be used successfully for the synthesis of poly-Si by laser annealing, at room temperature, and for n- and p-channel TFTs. The devices, fabricated according to CMOS compatible processes at 350 °C, showed field effect mobilities up to 8 and 2 cm2/(V s) for n- and p-type TFTs, respectively. The presented method combines a low-cost coating technique with the usage of recycled material, opening a route to a convenient and sustainable production of large-area, flexible, and even disposable/single-use electronics.

Flexible ultrathin-body single-photon avalanche diode sensors and CMOS integration.

We proposed the world's first flexible ultrathin-body single-photon avalanche diode (SPAD) as photon counting device providing a suitable solution to advanced implantable bio-compatible chronic medical monitoring, diagnostics and other applications. In this paper, we investigate the Geiger-mode performance of this flexible ultrathin-body SPAD comprehensively and we extend this work to the first flexible SPAD image sensor with in-pixel and off-pixel electronics integrated in CMOS. Experimental results show that dark count rate (DCR) by band-to-band tunneling can be reduced by optimizing multiplication doping. DCR by trap-assisted avalanche, which is believed to be originated from the trench etching process, could be further reduced, resulting in a DCR density of tens to hundreds of Hertz per micrometer square at cryogenic temperature. The influence of the trench etching process onto DCR is also proved by comparison with planar ultrathin-body SPAD structures without trench. Photon detection probability (PDP) can be achieved by wider depletion and drift regions and by carefully optimizing body thickness. PDP in frontside- (FSI) and backside-illumination (BSI) are comparable, thus making this technology suitable for both modes of illumination. Afterpulsing and crosstalk are negligible at 2µs dead time, while it has been proved, for the first time, that a CMOS SPAD pixel of this kind could work in a cryogenic environment. By appropriate choice of substrate, this technology is amenable to implantation for biocompatible photon-counting applications and wherever bended imaging sensors are essential.

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology.

We demonstrate a method for the low temperature growth (350 °C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-κ dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used.

Impact of the atomic layer deposition precursors diffusion on solid-state carbon nanotube based supercapacitors performances.

A study on the impact of atomic layer deposition (ALD) precursors diffusion on the performance of solid-state miniaturized nanostructure capacitor array is presented. Three-dimensional nanostructured capacitor array based on double conformal coating of multiwalled carbon nanotubes (MWCNTs) bundles is realized using ALD to deposit Al2O3 as dielectric layer and TiN as high aspect-ratio conformal counter-electrode on 2 µm long MWCNT bundles. The devices have a small footprint (from 100 µm(2) to 2500 µm(2)) and are realized using an IC wafer-scale manufacturing process with high reproducibility (≤0.3E-12F deviation). To evaluate the enhancement of the electrode surface, the measured capacitance values are compared to a lumped circuital model. The observed discrepancies are explained with a partial coating of the CNT, that determine a limited use of the available electrode surface area. To analyze the CNT coating effectiveness, the ALD precursors diffusions inside the CNT bundle is studied using a Knudsen diffusion mechanism.