Capacitance Contribution of NIH/3T3 Cells Existing on and between Electrodes of an Impedance Biosensor.

In this study, an impedance biosensor capable of real-time monitoring of the growth and drug reactions using NIH/3T3 cells was fabricated through a semiconductor process. With the fabricated impedance biosensor, the cell growth and drug reaction states are monitored in real-time, showing the validness of the developed biosensor. By using the developed impedance biosensor, we have investigated the capacitance contribution of NIH/3T3 cells existing on electrodes and between electrodes. To compare the capacitance value contributions of the cells on and between electrodes, wide- and narrow-gap electrode patterns are manufactured with 3.7 and 0.3 mm electrode gap spacings, respectively. From the detailed analysis, the capacitance contributions of NIH/3T3 cells existing on electrodes are estimated around less than 20 percent compared to the cells existing between electrodes. In other words, a minimized electrode area with maximized electrode spacing is the promising impedance biosensor design guide for accurate cell capacitance measurements.

Growth and Drug Interaction Monitoring of NIH 3T3 Cells by Image Analysis and Capacitive Biosensor.

Capacitive biosensors are manufactured on glass slides using the semiconductor process to monitor cell growth and cell-drug interactions in real time. Capacitance signals are continuously monitored for each 10 min interval during a 48 h period, with the variations of frequency from 1 kHz to 1 MHz. The capacitance values showed a gradual increase with the increase in NIH 3T3 cell numbers. After 48 h of growth, 6.67 µg/mL puromycin is injected for the monitoring of the cell-drug interaction. The capacitance values rapidly increased during a period of about 10 h, reflecting the rapid increase in the cell numbers. In this study, we monitored the state of cells and the cell-drug interactions using the developed capacitive biosensor. Additionally, we monitored the state of cell behavior using a JuLiTM Br&FL microscope. The monitoring of cell state by means of a capacitive biosensor is more sensitive than confluence measuring using a JuLiTM Br&FL microscope image. The developed capacitive biosensor could be applied in a wide range of bio-medical areas; for example, non-destructive real-time cell growth and cell-drug interaction monitoring.

A 3D Printable Electroconductive Biocomposite Bioink Based on Silk Fibroin-Conjugated Graphene Oxide.

Reduced graphene oxide (rGO) has wide application as a nanofiller in the fabrication of electroconductive biocomposites due to its exceptional properties. However, the hydrophobicity and chemical stability of rGO limit its ability to be incorporated into precursor polymers for physical mixing during biocomposite fabrication. Moreover, until now, no suitable rGO-combining biomaterials that are stable, soluble, biocompatible, and 3D printable have been developed. In this study, we fabricated digital light processing (DLP) printable bioink (SGOB1), through covalent reduction of graphene oxide (GO) by glycidyl methacrylated silk fibroin (SB). Compositional analyses showed that SGOB1 contains approximately 8.42% GO in its reduced state. Our results also showed that the rGO content of SGOB1 became more thermally stable and highly soluble. SGOB1 hydrogels demonstrated superior mechanical, electroconductive, and neurogenic properties than (SB). Furthermore, the photocurable bioink supported Neuro2a cell proliferation and viability. Therefore, SGOB1 could be a suitable biocomposite for neural tissue engineering.

Hole Mobility Characteristics with Surface Roughness on Silicon-on-Insulator Substrate.

Hole mobility characteristics were investigated with surface roughness and silicon-on-insulator (SOI) thickness variations to investigate the influence of surface roughness to mobility. The root mean square roughness varied between 0.16, 0.85 and 10.6 nm in 220, 100 and 40 nm thick SOI samples. Hole mobility was measured and analyzed as a function of effective field and temperature with the variations of surface roughness. The hole mobility, determined by transconductance, greatly decreased with the increase of effective field due to the increased surface roughness scattering in 40 nm thick SOI samples. On the other hand, phonon scattering was a dominant mechanism with the increase of temperature, irrespective of surface roughness and SOI thickness. The induced surface roughness of the devices increases the phonon scattering, thereby reducing the electron and hole mobility. The hole mobility decreases with the roughening of the samples, with the increase of temperature due to increased phonon scattering. Therefore, for enhanced mobility, surface scattering and phonon scattering should be controlled even in atomic scale roughened samples.

Highly Ordered Microscale-Pyramidal-Structure-Arrayed Silicon Membranes for Filter Applications.

Microscale-pyramidal-structure-arrayed patterned silicon membranes are manufactured using semiconductor processes and potassium hydroxide (KOH) etching techniques for filter applications. The silicon nitride on silicon on the insulator wafer functions as a masking layer, and the roughness of the silicon (100) plane strongly depends on the etching temperature and KOH concentration. To fabricate the membrane filter, a series of dry and wet etching using 45 wt% KOH solutions at the constant temperature of 70 °C was performed. With the dry and wet etching, micro-pyramidal arrays with 300 µm top and 16-20 µm bottom opening sizes were created. The morphological structures were analyzed using scanning electron microscopy. The manufactured membranes were tested as optical directional filters and particle filters.

Scalability of Schottky barrier metal-oxide-semiconductor transistors.

In this paper, the general characteristics and the scalability of Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are introduced and reviewed. The most important factors, i.e., interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are estimated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are estimated as 1.5 × 1013 traps/cm2, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by N2 annealing. Based on the diode characteristics, various sizes of erbium-silicided/platinum-silicided n/p-type SB-MOSFETs are manufactured and analyzed. The manufactured SB-MOSFETs show enhanced drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are comparable with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

Silicide/Silicon Hetero-Junction Structure for Thermoelectric Applications.

We fabricated silicide/silicon hetero-junction structured thermoelectric device by CMOS process for the reduction of thermal conductivity with the scatterings of phonons at silicide/silicon interfaces. Electrical conductivities, Seebeck coefficients, power factors, and temperature differences are evaluated using the steady state analysis method. Platinum silicide/silicon multilayered structure showed an enhanced Seebeck coefficient and power factor characteristics, which was considered for p-leg element. Also, erbium silicide/silicon structure showed an enhanced Seebeck coefficient, which was considered for an n-leg element. Silicide/silicon multilayered structure is promising for thermoelectric applications by reducing thermal conductivity with an enhanced Seebeck coefficient. However, because of the high thermal conductivity of the silicon packing during thermal gradient is not a problem any temperature difference. Therefore, requires more testing and analysis in order to overcome this problem. Thermoelectric generators are devices that based on the Seebeck effect, convert temperature differences into electrical energy. Although thermoelectric phenomena have been used for heating and cooling applications quite extensively, it is only in recent years that interest has increased in energy generation.

Carrier Transport Properties of Bilayer Graphene Obtained via Hall Measurements.

The electron transport characteristics of bilayer graphene were investigated in terms of changes in the temperature from 2 to 300 K. The purpose of this study was a confirming the reported values5 of the carrier density and the mobility for using a ballistic quantum transport experiment. The mechanical exfoliation method was adopted to get the best quality of bilayer graphene and the number of layers of graphene was identified by the Raman spectra. Our bilayer graphene was a slightly n-doped state with the neutrality point at Vg = -7.5 V. Hall measurements provided an accurate means to evaluate the carrier density and the mobility. In magnetic field of -9 to 9 T, clear Shubnikov-de Haas oscillations were measured in bilayer graphene, indicating the presence of a clear electron quantum transport mechanism. The mobility and the carrier density of the bilayer graphene at 2 K were measured to be 9,400 cm2/V·s and 3 x 10(11) cm(-2), respectively.

The influence of ionized impurity scattering on the thermopower of Si nanowires.

The thermopower of Si nanowires was investigated on the basis of electronic transport theory, taking into account ionized impurity scattering as well as electron-phonon scattering. It was found that the enhancement of the Seebeck coefficient in nanowires arising from quantum confinement is unimportant due to the ionized impurity scattering associated with donor deactivation. Furthermore, because the electrical conductivity is degraded significantly as the nanowire size becomes smaller, despite the accompanying slightly enhanced Seebeck coefficient, the reduction of the nanowire size is not beneficial, at least for the thermopower of devices.

Seebeck coefficient characterization of highly doped n- and p-type silicon nanowires for thermoelectric device applications fabricated with top-down approach.

A silicon nanowire one-dimensional thermoelectric device is presented as a solution to enhance thermoelectric performance. A top-down process is adopted for the definition of 50 nm silicon nanowires (SiNWs) and the fabrication of the nano-structured thermoelectric devices on silicon on insulator (SOl) wafer. To measure the Seebeck coefficients of 50 nm width n- and p-type SiNWs, a thermoelectric test structure, containing SiNWs, micro-heaters and temperature sensors is fabricated. Doping concentration is 1.0 x 10(20) cm(-3) for both for n- and p-type SiNWs. To determine the temperature gradient, a temperature coefficient of resistance (TCR) analysis is done and the extracted TCR value is 1750-1800 PPM x K(-1). The measured Seebeck coefficients are -127.583 microV x K(-1) and 141.758 microV x K(-1) for n- and p-type SiNWs, respectively, at room temperature. Consequently, power factor values are 1.46 mW x m(-1) x K(-2) and 1.66 mW x m(-1) x K(-2) for n- and p-type SiNWs, respectively. Our results indicate that SiNWs based thermoelectric devices have a great potential for applications in future energy conversion systems.

Effect of silicide/silicon hetero-junction structure on thermal conductivity and Seebeck coefficient.

We fabricated a thermoelectric device with a silicide/silicon laminated hetero-structure by using RF sputtering and rapid thermal annealing. The device was observed to have Ohmic characteristics by I-V measurement. The temperature differences and Seebeck coefficients of the proposed silicide/silicon laminated and bulk structure were measured. The laminated thermoelectric device shows suppression of heat flow from the hot to cold side. This is supported by the theory that the atomic mass difference between silicide and silicon creates a scattering center for phonons. The major impact of our work is that phonon transmission is suppressed at the interface between silicide and silicon without degrading electrical conductivity. The estimated thermal conductivity of the 3-layer laminated device is 126.2 +/- 3.7 W/m. K. Thus, by using the 3-layer laminated structure, thermal conductivity is reduced by around 16% compared to bulk silicon. However, the Seebeck coefficient of the thermoelectric device is degraded compared to that of bulk silicon. It is understood that electrical conductivity is improved by using silicide as a scattering center.

Electronic transport of lateral PtSi/n/n+-Si Schottky diodes.

We investigated the transport properties of a lateral PtSi/n/n(+)-Si Schottky diode prepared on an n-type silicon-on-insulator (SOI) wafer with a special attention on the bipolar transport and the surface effect. With applying a back-gate bias changing from +18 V to -18 V, the unipolar transport behavior switched over to the bipolar one, where an enhanced surface recombination rate due to a high surface-to-volume ratio produced a current density approximately 3 x 10(3) A/cm2 for 2 V bias through a 40 nm-thick and 18 microm-long nanoribbon. The recombination time was estimated to be approximately 1 micros from independent CV measurements, which is much smaller value than that of a bulk. The local Fermi energy level for electrons at the channel center was monitored by an additional voltage probe during each I(D)-V(D) measurement and it revealed the intricate nature of the bipolar transport manifested by the huge asymmetrical hysteretic behavior on a drain bias cycle which is attributed to the charge storage effect and asymmetrical junction profiles.

Evaluation of Seebeck coefficients in n- and p-type silicon nanowires fabricated by complementary metal-oxide-semiconductor technology.

Silicon-based thermoelectric nanowires were fabricated by using complementary metal-oxide-semiconductor (CMOS) technology. 50 nm width n- and p-type silicon nanowires (SiNWs) were manufactured using a conventional photolithography method on 8 inch silicon wafer. For the evaluation of the Seebeck coefficients of the silicon nanowires, heater and temperature sensor embedded test patterns were fabricated. Moreover, for the elimination of electrical and thermal contact resistance issues, the SiNWs, heater and temperature sensors were fabricated monolithically using a CMOS process. For validation of the temperature measurement by an electrical method, scanning thermal microscopy analysis was carried out. The highest Seebeck coefficients were - 169.97 µV K(-1) and 152.82 µV K(-1) and the highest power factors were 2.77 mW m(-1) K(-2) and 0.65 mW m(-1) K(-2) for n- and p-type SiNWs, respectively, in the temperature range from 200 to 300 K. The larger power factor value for n-type SiNW was due to the higher electrical conductivity. The total Seebeck coefficient and total power factor for the n- and p-leg unit device were 157.66 µV K(-1) and 9.30 mW m(-1) K(-2) at 300 K, respectively.

Top-down processed silicon nanowires for thermoelectric applications.

50 nm wide n-type silicon nanowires have been manufactured by using a top-down process in order to investigate the thermoelectric properties of silicon nanowire. Nanowire test structures with platinum heaters and temperature sensors were fabricated. The extracted temperature coefficient of resistance (TCR) of the temperature sensors was 786.6 PPM/K. Also, the extracted Seebeck coefficient and power factor of the 50 nm wide phosphorus doped n-type silicon nanowires were -118 miroV/K and 2.16 mW x K(-2) x m(-1).

Electrical characterization of n/p-type nickel silicide/silicon junctions by Sb segregation.

In this paper, n/p-type nickel-silicided Schottky diodes were fabricated by incorporating antimony atoms near the nickel silicide/Si junction interface and the electrical characteristics were studied through measurements and simulations. The effective Schottky barrier height (SBH) for electron, extracted from the thermionic emission model, drastically decreased from 0.68 to less than 0.1 eV while that for hole slightly increased from 0.43 to 0.53 eV. In order to identify the current conduction mechanisms, the experimental current-temperature-voltage characteristics for the n-type diode were fitted based on various models for transport of charge carrier in Schottky diodes. As the result, the large change in effective SBH for electron is ascribed to trap-assisted tunneling rather than barrier height inhomogeneity.

The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process.

Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 µV/K for p-leg and -94 µV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K(2) at room temperature.