Accurate Evaluation of Electro-Thermal Performance in Silicon Nanosheet Field-Effect Transistors with Schemes for Controlling Parasitic Bottom Transistors.

The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat's impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (TSD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (Cgg) as the TSD increases. A higher TIS height prevents the Cgg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (CL) increases. As CL increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling trpbt and improving electro-thermal performance in sub-3 nm node NSFETs.

A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs.

This study proposed a novel source/drain (S/D) extension scheme to increase the stress in nanosheet (NS) field-effect transistors (NSFETs) and investigated the scheme by using technology-computer-aided-design simulations. In three-dimensional integrated circuits, transistors in the bottom tier were exposed to subsequent processes; therefore, selective annealing, such as laser-spike annealing (LSA), should be applied. However, the application of the LSA process to NSFETs significantly decreased the on-state current (Ion) owing to diffusionless S/D dopants. Furthermore, the barrier height below the inner spacer was not lowered even under on-state bias conditions because ultra-shallow junctions between the NS and S/D were formed far from the gate metal. However, the proposed S/D extension scheme overcame these Ion reduction issues by adding an NS-channel-etching process before S/D formation. A larger S/D volume induced a larger stress in the NS channels; thus, the stress was boosted by over 25%. Additionally, an increase in carrier concentrations in the NS channels improved Ion. Therefore, Ion increased by approximately 21.7% (37.4%) in NFETs (PFETs) compared with NSFETs without the proposed scheme. Additionally, the RC delay was improved by 2.03% (9.27%) in NFETs (PFETs) compared with NSFETs using rapid thermal annealing. Therefore, the S/D extension scheme overcame the Ion reduction issues encountered in LSA and significantly enhanced the AC/DC performance.

Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors.

The inner spacer thickness (TIS) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable TIS variation (ΔTIS). The gate length (LG) depends on the TIS. Thus, the DC/AC performance is significantly affected by ΔTIS. Because the effects of ΔTIS on the performance depend on which inner spacer is varied, the sensitivities of the performance to the top, middle, and bottom (T, M, and B, respectively) ΔTIS should be studied separately. In addition, the source/drain (S/D) recess process variation that forms the parasitic bottom transistor (trpbt) should be considered with ΔTIS because the gate controllability over trpbt is significantly dependent on ΔTIS,B. If the S/D recess depth (TSD) variation cannot be completely eliminated, reducing ΔTIS,B is crucial for suppressing the effects of trpbt. It is noteworthy that reducing ΔTIS,B is the most important factor when the TSD variation occurs, whereas reducing ΔTIS,T and ΔTIS,M is crucial in the absence of TSD variation to minimize the DC performance variation. As the TIS increases, the gate capacitance (Cgg) decreases owing to the reduction in both parasitic and intrinsic capacitance, but the sensitivity of Cgg to each ΔTIS is almost the same. Therefore, the difference in performance sensitivity related to AC response is also strongly affected by the DC characteristics. In particular, since TSD of 5 nm increases the off-state current (Ioff) sensitivity to ΔTIS,B by a factor of 22.5 in NFETs, the ΔTIS,B below 1 nm is essential for further scaling and yield enhancement.

Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15-22 nm) Nanowire FETs with Various Channel Diameters.

In this study, threshold voltage (Vth) variability was investigated in silicon nanowire field-effect transistors (SNWFETs) with short gate-lengths of 15-22 nm and various channel diameters (DNW) of 7, 9, and 12 nm. Linear slope and nonzero y-intercept were observed in a Pelgrom plot of the standard deviation of Vth (σVth), which originated from random and process variations. Interestingly, the slope and y-intercept differed for each DNW, and σVth was the smallest at a median DNW of 9 nm. To analyze the observed DNW tendency of σVth, a novel modeling approach based on the error propagation law was proposed. The contribution of gate-metal work function, channel dopant concentration (Nch), and DNW variations (WFV, ∆Nch, and ∆DNW) to σVth were evaluated by directly fitting the developed model to measured σVth. As a result, WFV induced by metal gate granularity increased as channel area increases, and the slope of WFV in Pelgrom plot is similar to that of σVth. As DNW decreased, SNWFETs became robust to ∆Nch but vulnerable to ∆DNW. Consequently, the contribution of ∆DNW, WFV, and ∆Nch is dominant at DNW of 7 nm, 9 nm, and 12, respectively. The proposed model enables the quantifying of the contribution of various variation sources of Vth variation, and it is applicable to all SNWFETs with various LG and DNW.

Threshold Voltage Variations Induced by Si1-xGex and Si1-xCx of Sub 5-nm Node Silicon Nanosheet Field-Effect Transistors.

In this paper, we investigated the threshold voltage (Vth) variations in sub 5-nm node silicon nanosheet FETs (NSFETs) caused by Ge and C diffusion into NS channels using fully-calibrated 3-D TCAD simulation. Ge (C) atoms of Si1-xGex (Si1-xCx) source/drain (S/D) diffuse toward the NS channels in lateral direction in p-type (n-type) FETs, and Ge atoms of Si0.7Ge0.3 stacks diffuse toward the NS channels in vertical direction. Increasing Ge mole fraction of the Si1-xGex S/D in the p-type FETs (PFETs) causing increasing compressive channel stress retards boron dopants diffusing from the Si1-xGex S/D into the NS channels, thus increasing the Vth of PFETs (Vth, p). However, the Vth, p decreases as the Ge mole fraction of the Si1-xGex S/D becomes greater than 0.5 due to the higher valence band energy (Ev) of the NS channels. On the other hand, the Vth of n-type FETs (NFETs) (Vth, n) consistently increases as the C mole fraction of the Si1-xCx S/D increases due to monotonously retarded phosphorus dopants diffusing from the Si1-xCx S/D into the NS channels. On the other hand, the Vth, p and Vth, n consistently decreases and increases, respectively, as Si/Si0.7Ge0.3 intermixing becomes severer because both Ev and conduction band energies (Ec) of the NS channels become higher. In addition, the Vth, p variations are more sensitive to the Si/Si0.7Ge0.3 intermixing than the Vth, n variations because the Ge mole fraction in NS channels affects the Ev remarkably rather than the Ec. As a result, the Ge atoms diffusing toward the NS channels should be carefully considered more than the C diffusion toward the NS channels for fine Vth variation optimization in sub 5-nm node NSFETs.

Piperine ameliorates the severity of cerulein-induced acute pancreatitis by inhibiting the activation of mitogen activated protein kinases.

Piperine is a phenolic component of black pepper (Piper nigrum) and long pepper (Piper longum), fruits used in traditional Asian medicine. Our previous study showed that piperine inhibits lipopolysaccharide-induced inflammatory responses. In this study, we investigated whether piperine reduces the severity of cerulein-induced acute pancreatitis (AP). Administration of piperine reduced histologic damage and myeloperoxidase (MPO) activity in the pancreas and ameliorated many of the examined laboratory parameters, including the pancreatic weight (PW) to body weight (BW) ratio, as well as serum levels of amylase and lipase and trypsin activity. Furthermore, piperine pretreatment reduced the production of tumor necrosis factor (TNF)-α, interleukin (IL)-1ß, and IL-6 during cerulein-induced AP. In accordance with in vivo results, piperine reduced cell death, amylase and lipase activity, and cytokine production in isolated cerulein-treated pancreatic acinar cells. In addition, piperine inhibited the activation of mitogen-activated protein kinases (MAPKs). These findings suggest that the anti-inflammatory effect of piperine in cerulein-induced AP is mediated by inhibiting the activation of MAPKs. Thus, piperine may have a protective effect against AP.

Changes in brain activation induced by the training of hypothesis generation skills: an fMRI study.

The aim of the present study is to investigate the learning-related changes in brain activation induced by the training of hypothesis generation skills regarding biological phenomena. Eighteen undergraduate participants were scanned twice with functional magnetic resonance imaging (fMRI) before and after training over a period of 2 months. The experimental group underwent eight biological hypothesis generation training programs, but the control group was not given any during the 2-month period. The results showed that the left frontal gyri, the cingulate gyrus, and the cuneus were activated during hypothesis generation. In addition, the brain activation of the trained group increased in the left inferior and the superior frontal gyri, which are related to working memory load and higher-order inferential processes. However, the activation after training decreased in the occipito-parietal route, which is associated with the perception and the analysis processes of visual information. Furthermore, the results have suggested that the dorsolateral prefrontal cortex (DLPFC) region is the critical area in the training of hypothesis generation skills.

Increased information transmission during scientific hypothesis generation: mutual information analysis of multichannel EEG.

Hypothesis generation has been regarded as one of the core reasoning processes in creative thinking and scientific discovery. To investigate changes in the amount of information transmission during scientific hypothesis generation, the averaged cross-mutual-information (A-CMI) of EEGs was estimated. Twenty-five 5th grade students were sampled in this study. EEG signals from 16 electrodes on each subject's scalp were recorded using a 32-channel EEG system. In order to generate hypotheses, the students were asked to observe 20 quail eggs that gave rise to questions such as: Why do different sizes and shapes of patterns appear on the surface of the eggs? After the observation, they were asked to generate a scientific hypothesis-a tentative causal explanation for the evoked question. The results of experimentation indicated several distinct brain activities during hypothesis generation interacting between different local brain regions. In addition, it was observed that the amount of information transmission during hypothesis generation increased in a large part of the brain region encompassing the temporal, parietal, and occipital cortexes, which implies the use of declarative and procedural memory systems. Furthermore, this study suggested the possibility that neuropsychological approaches may be potential tools to investigate the neuronal activity of EEGs during hypothesis generation.

Differences in brain information transmission between gifted and normal children during scientific hypothesis generation.

The purpose of the present study was to investigate differences in neural information transmission between gifted and normal children involved in scientific hypothesis generation. To investigate changes in the amount of information transmission, the children's averaged-cross mutual information (A-CMI) of EEGs was estimated during their generation of scientific hypotheses. We recorded EEG from 25 gifted and 25 age-matched normal children using 16 electrodes on each subject's scalp. To generate hypotheses, the children were asked to observe 20 "quail eggs" that gave rise to questions. After observation, they were asked to generate a scientific hypothesis--a tentative causal explanation for the questions evoked. The results of this study revealed several distinguishing brain activities between gifted and normal children during hypothesis generation. In contrast to normal children, gifted children showed increased A-CMI values between the left temporal and central, between the left temporal and parietal, and between the left central and parietal locations while generating a hypothesis. These results suggested that gifted children more efficiently distribute the cognitive resources essential to cope with hypothesis generation.