Notched Anchor Design for Low Voltage Operation of Nanoelectromechanical (NEM) Memory Switches.

Because nanoelectromechanical (NEM) memory switches generally have higher pull-in voltage (VPI) and lower reliability than CMOS devices, reducing VPI and maximum stress (σMAX) of NEM memory switches have been critical issues for the implementation of monolithic-3D (M3D) CMOS-NEM hybrid reconfigurable logic (RL) circuits. In this paper, a novel notched anchor design is proposed to reduce the VPI and σMAX of NEM memory switches. Moreover, the novel design has an advantage in terms of chip density over the conventional design under the same VPI condition. In the case of our proposed NEM memory switches, their anchors are placed in the vias of metal interconnection layers. Thus, even if notched patterns are formed on the anchors, it will be helpful to effectively increase beam length, which eventually lowers VPI and σMAX. In this manuscript, the proposed notched anchor design has been confirmed by finite-element-method (FEM) simulation. According to the simulation results, the proposed notched anchor design lowers VPI by ~23% and σMAX by ~24%.

Active Region Formation of Nanoelectromechanical (NEM) Devices for Complementary-Metal-Oxide-Semiconductor-NEM Co-Integration.

Considering the isotropic release process for nanoelectromechanical (NEM) devices, defining the specific sacrificial layer of the inter-metal-dielectric (IMD), i.e., the active region only for NEM devices, is one of the most important issue for complementary-metal-oxide-semiconductor-NEM (CMOS-NEM) co-integrated circuits. In this paper, novel fabrication method to define the active region of NEM devices is proposed by forming the trenched mesa-shape pattern in the IMD and depositing aluminum oxide (Al2O3) protecting layer. By applying the proposed process, the void space for mechanical operation of NEM devices can be formed user-controllably without the damage and collapse of CMOS part located below the NEM part. The feasibility of the proposed process is verified by fabricating and measuring the proof-of-concept prototype consists of the aluminum (Al) interconnects, silicon dioxide (SiO2) IMD and NEM memory switches.

Encapsulation of NEM Memory Switches for Monolithic-Three-Dimensional (M3D) CMOS⁻NEM Hybrid Circuits.

Considering the isotropic release process of nanoelectromechanical systems (NEMSs), defining the active region of NEM memory switches is one of the most challenging process technologies for the implementation of monolithic-three-dimensional (M3D) CMOS⁻NEM hybrid circuits. In this paper, we propose a novel encapsulation method of NEM memory switches. It uses alumina (Al2O3) passivation layers which are fully compatible with the CMOS baseline process. The Al2O3 bottom passivation layer can protect intermetal dielectric (IMD) and metal interconnection layers from the vapor hydrogen fluoride (HF) etching process. Thus, the controllable formation of the cavity for the mechanical movement of NEM devices can be achieved without causing any damage to CMOS baseline circuits as well as metal interconnection lines. As a result, NEM memory switches can be located in any place and metal layer of an M3D CMOS⁻NEM hybrid chip, which makes circuit design easier and more volume efficient. The feasibility of our proposed method is verified based on experimental results.