Effects of Electrode Thickness on Three-Dimensional NiCrAl Metal Foam Cathode for Lithium Ion Battery.

LiFePO4 electrodes using three dimensional NiCrAl alloy metal foam of different electrode thickness are prepared. In order to improve the electrochemical and cycle-life performance of lithium ion batteries, it is important to optimize the electrode thickness and mass loading of active material. As compared to those with thick electrode, the cells with thin electrode exhibit high rate performance and cycle-life behavior, due to the shorter diffusion length of lithium-ion and improved kinetic behavior. Also, cyclic voltammetry curves and electrochemical impedance spectroscopy analysis indicate that the redox reaction for the thinner electrode occurs much faster, and the charge transfer resistance is much lower. The results of same current density (mA cm-2) show that 450 µm-thickness electrode exhibits superior electrochemical and power performance. It is because the 300 µm-thickness electrode which has the lowest mass loading of active material meant that it carried the highest current rate, and thicker electrodes show higher internal resistance and much poorer kinetic property. Namely, electrode thickness and an amount of active material are difference according to the intended use.

Characterization of Lateral Structure of the p-i-n Diode for Thin-Film Silicon Solar Cell.

The lateral structure of the p-i-n diode was characterized for thin-film silicon solar cell application. The structure can benefit from a wide intrinsic layer, which can improve efficiency without increasing cell thickness. Compared with conventional thin-film p-i-n cells, the p-i-n diode lateral structure exploited direct light irradiation on the absorber layer, one-side contact, and bifacial irradiation. Considering the effect of different carrier lifetimes and recombinations, we calculated efficiency parameters by using a commercially available simulation program as a function of intrinsic layer width, as well as the distance between p/i or n/i junctions to contacts. We then obtained excellent parameter values of 706.52 mV open-circuit voltage, 24.16 mA/Cm2 short-circuit current, 82.66% fill factor, and 14.11% efficiency from a lateral cell (thickness = 3 µm; intrinsic layer width = 53 µm) in monofacial irradiation mode (i.e., only sunlight from the front side was considered). Simulation results of the cell without using rear-side reflector in bifacial irradiation mode showed 11.26% front and 9.72% rear efficiencies. Our findings confirmed that the laterally structured p-i-n cell can be a potentially powerful means for producing highly efficient, thin-film silicon solar cells.

50-nm Nano-Scaled Vertical-Transistor with NiSi2 Seed-Induced Vertically Crystallized Poly-Silicon Channel for Very-Large-Scale-Integration.

Vertical-channel MOSFETs are hard to demonstrate a high electrical performance than the planar MOSFETs because of its polycrystalline-silicon (poly-Si) channel for 3-D CMOS ICs. In this paper, we have demonstrated a vertical poly-silicon-channel (VPSC) transistor NiSi2 seed-induced vertical crystallization (SIVC) and compared with the typical SG-VPC MOSFETs with solid-phase crystallization (SPC). The SIVC poly-Si showed large longitudinal grains with low defect trap sites, while the SPC poly-Si showed small spherical grains with large defect trap sites. Therefore, the electrical performance of SG-VPC MOSFETs with SIVC was superior to the SG-VPC MOSFETs with SPC in all aspects.

Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor.

Realizing a low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) with sub-kT/q subthreshold slope (SS) is significantly important to the development of next generation active-matrix organic-light emitting diode displays. This is the first time a sub-kT/q SS (31.44 mV/dec) incorporated with a LTPS-TFT with polycrystalline-Pb(Zr,Ti)O3 (PZT)/ZrTiO4 (ZTO) gate dielectrics has been demonstrated. The sub-kT/q SS was observed in the weak inversion region at -0.5 V showing ultra-low operating voltage with the highest mobility (250.5 cm(2)/Vsec) reported so far. In addition, the reliability of DC negative bias stress, hot carrier stress and self-heating stress in LTPS-TFT with negative capacitance was investigated for the first time. It was found that the self-heating stress showed accelerated SS degradation due to the PZT Curie temperature.

Integrating Epitaxial-Like Pb(Zr,Ti)O3 Thin-Film into Silicon for Next-Generation Ferroelectric Field-Effect Transistor.

The development of ferroelectric random-access memory (FeRAM) technology with control of grain boundaries would result in a breakthrough for new nonvolatile memory devices. The excellent piezoelectric and electrical properties of bulk ferroelectrics are degraded when the ferroelectric is processed into thin films because the grain boundaries then form randomly. Controlling the nature of nucleation and growth are the keys to achieving a good crystalline thin-film. However, the sought after high-quality ferroelectric thin-film has so far been thought to be impossible to make, and research has been restricted to atomic-layer deposition which is extremely expensive and has poor reproducibility. Here we demonstrate a novel epitaxial-like growth technique to achieve extremely uniform and large rectangular-shaped grains in thin-film ferroelectrics by dividing the nucleation and growth phases. With this technique, it is possible to achieve 100-µm large uniform grains, even made available on Si, which is large enough to fabricate a field-effect transistor in each grain. The electrical and reliability test results, including endurance and retention test results, were superior to other FeRAMs reported so far and thus the results presented here constitute the first step toward the development of FeRAM using epitaxial-like ferroelectric thin-films.

Electrical stress effect on on-current of MILC poly-Si thin-film transistors.

In this study, we studied the effect of the electrical stress on the on-current of metal-induced laterally crystallized poly-Si TFTs. It was found that the electrical performance of polycrystalline silicon thin-film transistors (TFTs) is greatly affected by the electrical stress. Under the electrical stress condition, the drain current increases due to hot-electron trap at the drain junction. The computer simulation revealed the fact that the improvement mechanism can be reproduced by effective channel length shortening. It turns out that analysis of the capacitance and output characteristics supports this model.

Tilted back exposure for lightly doped drain structure in metal induced lateral crystallization poly Si thin film transistors.

It has been known that LDD is essential to reduce the leakage current in poly TFTs, which has been regarded as one of the most important issues in poly TFT characteristics. However, according to the conventional process, an extra mask is needed solely for the LDD formation, which is not only complicated but also difficult to maintain the reproducibility. In this work, a simple method has been introduced for formation of LDD structure in poly Si TFTs, Tilted Back Exposure (TBE) technique. It has been found that asymmetry patterns can be realized with TBE process and submicron accuracy can be easily achieved by adjusting the angle between the substrate and light source. The LDD TFTs using TBE process shows almost the same electrical properties as the LDD TFTs using an additional separate LDD Mask.

Charge retention characteristics of silicide-induced crystallized polycrystalline silicon floating gate thin-film transistors for active matrix organic light-emitting diode.

In this work, non-volatile memory thin-film transistor (NVM-TFT) was fabricated by nickel silicide-induced laterally crystallized (SILC) polycrystalline silicon (poly-Si) as the active layer. The nickel seed silicide-induced crystallized (SIC) poly-Si was used as storage layer which is embedded in the gate insulator. The novel unit pixel of active matrix organic light-emitting diode (AMOLED) using NVM-TFT is proposed and investigated the electrical and optical performance. The threshold voltage shift showed 17.2 V and the high reliability of retention characteristic was demonstrated until 10 years. The retention time can modulate the recharge refresh time of the unit pixel of AMOLED up to 5000 sec.

Electrical activation of ion mass doped phosphorous.

In this study, three different crystalline states of silicon were prepared to be doped with phosphorous by IMD, amorphous, poly crystalline and single crystalline silicon. The dose was controlled by IMD duration time and heat treatment for electrical activation was done in RTA and Furnace. In case of RTA, annealing temperature was controlled by the duration time of power application. In case of a single crystal substrate, the resistance was measured to be 20-50 omega/square depending on the dose and annealing temperature. In case of poly crystal, we could observe segregation of the dopant at grain boundaries, which caused increase of the resistance with increase of annealing temperature. In case of amorphous silicon thin film, this phenomenon could not be observed due to lack of the grain boundaries and the minimum resistance of this work was about 300 omega/square, which was about the same to that in a poly silicon thin film.

Leakage current behavior of the bottom gate poly thin-film transistor fabricated by copper damascene process.

Bottom-gated polycrystalline-silicon (poly-Si) thin-film transistors (TFT's) with a planarized copper (Cu) gate for large-area displays have been fabricated and characterized. The 500 nm depth of trenchs are filled up with 400 nm, 500 nm, 600 nm thickness of Cu using the damascene process of VLSI technology, poly-Si TFT's with 100 nm thick gate insulator are fabricated on the Cu gate. As the Cu gate's thickness becomes thinner, the anomalous leakage current of poly-Si TFT's is reduced significantly both before and after electrical stressing. The results simulated by 3D electric field simulator demonstrate that the structure of planarized gate in bottom-gate TFT can effectively reduce the electric field causing the field emission between the gate and the drain.

Effect of lightly doped drain structure on P-channel metal induced lateral crystallization thin film transistors.

A Lightly Doped Drain (LDD) structure is known to be very effective in preventing hot electrons in modern NMOS transistors. In this work, the lightly doped region was formed in poly TFT by using a separate LDD mask aligned to a gate mask. The misalignment can be calculated to be about 1.5 microm, and depending on the location of the V(d) application between the source and drain, an LDD or Lightly Doped Source (LDS) structure can be realized on the same TFT. In this way, we can make a perfect comparison between these two structures. It turned out that the LDD is mainly responsible for the low leakage current, and no more than 0.5 microm of the lightly doped region is necessary to lower the leakage current down to less than 5 x 10(-11) amps at V(d) = 10 volts. Typically, the on-current of MILC TFT is more than 10(-4) amps, but 2.5 microm LDS decreases it to below 10(-7) amps.

Electrical stress effect on the leakage current of metal-induced laterally crystallized p-channel poly-Si TFTs.

A p-type polycrystalline silicon thin-film transistor (TFT) was fabricated using the metal-induced lateral crystallization (MILC) technique at 550 degrees C. To reduce the leakage current in the MILC TFT, electrical stress (ES), newly developed in this work, was applied prior to the I(D)-V(G) measurements. It was found that ES is effective only when the TFT is under off-state. The stress gate voltage is related to the leakage current at high gate voltages and the electric field between the source and the drain to the leakage current at low gate voltages. The leakage current of the MILC TFT could be lowered to 10(-11) A for width/length ratios of 1/2 measured at the drain voltage of 3 V. A new plausible model has been suggested to explain the ES effect on the leakage current behavior in low-temperature polycrystalline silicon TFTs.