Chemically induced Fermi level pinning effects of high-k dielectrics on graphene.

High-k materials such as Al2O3 and HfO2 are widely used as gate dielectrics in graphene devices. However, the effective work function values of metal gate in graphene FET are significantly deviated from their vacuum work function, which is similar to the Fermi level pinning effect observed in silicon MOSFETs with high-k dielectric. The degree of deviation represented by a pinning factor was much worse with HfO2 (pinning factor (S) = 0.19) than with Al2O3 (S = 0.69). We propose that the significant pinning-like behaviors induced by HfO2 are correlated with the oxygen exchange reactions occurred at the interface of graphene and HfO2.

Demonstration of Complementary Ternary Graphene Field-Effect Transistors.

Strong demand for power reduction in state-of-the-art semiconductor devices calls for novel devices and architectures. Since ternary logic architecture can perform the same function as binary logic architecture with a much lower device density and higher information density, a switch device suitable for the ternary logic has been pursued for several decades. However, a single device that satisfies all the requirements for ternary logic architecture has not been demonstrated. We demonstrated a ternary graphene field-effect transistor (TGFET), showing three discrete current states in one device. The ternary function was achieved by introducing a metal strip to the middle of graphene channel, which created an N-P-N or P-N-P doping pattern depending on the work function of the metal. In addition, a standard ternary inverter working at room temperature has been achieved by modulating the work function of the metal in a graphene channel. The feasibility of a ternary inverter indicates that a general ternary logic architecture can be realized using complementary TGFETs. This breakthrough will provide a key stepping-stone for an extreme-low-power computing technology.

A facile process to achieve hysteresis-free and fully stabilized graphene field-effect transistors.

The operation of chemical vapor-deposited (CVD) graphene field-effect transistors (GFETs) is highly sensitive to environmental factors such as the substrate, polymer residues, ambient condition, and other species adsorbed on the graphene surface due to their high defect density. As a result, CVD GFETs often exhibit a large hysteresis and time-dependent instability. These problems become a major roadblock in the systematic study of graphene devices. We report a facile process to alleviate these problems, which can be used to fabricate stable high performance CVD GFETs with symmetrical current-voltage (I-V) characteristics and an effective carrier mobility over 6000 cm(2) V(-1) s(-1). This process combined a few steps of processes in sequence including pre-annealing in a vacuum, depositing a passivation layer, and the final annealing in a vacuum, and eliminated ∼50% of charging sources primarily originating from water reduction reactions.

Quantitatively estimating defects in graphene devices using discharge current analysis method.

Defects of graphene are the most important concern for the successful applications of graphene since they affect device performance significantly. However, once the graphene is integrated in the device structures, the quality of graphene and surrounding environment could only be assessed using indirect information such as hysteresis, mobility and drive current. Here we develop a discharge current analysis method to measure the quality of graphene integrated in a field effect transistor structure by analyzing the discharge current and examine its validity using various device structures. The density of charging sites affecting the performance of graphene field effect transistor obtained using the discharge current analysis method was on the order of 10(14)/cm(2), which closely correlates with the intensity ratio of the D to G bands in Raman spectroscopy. The graphene FETs fabricated on poly(ethylene naphthalate) (PEN) are found to have a lower density of charging sites than those on SiO2/Si substrate, mainly due to reduced interfacial interaction between the graphene and the PEN. This method can be an indispensable means to improve the stability of devices using a graphene as it provides an accurate and quantitative way to define the quality of graphene after the device fabrication.