ABSTRACT
By a sol-gel method, a BiFeO3 (BFO) capacitor is fabricated and connected with the control thin film transistor (TFT). Compared with a control thin-film transistor, the proposed BFO TFT achieves 56% drive current enhancement and 7-28% subthreshold swing (SS) reduction. Moreover, the effect of the proposed BiFeO3 capacitor on IDS-VGS hysteresis in the BFO TFT is 0.1-0.2 V. Because dVint/dVGS > 1 is obtained at a wide range of VGS, it reveals that the incomplete dipole flipping is a major mechanism to obtain improved SS and a small hysteresis effect in the BFO TFT. Experimental results indicate that sol-gel BFO TFT is a potential candidate for digital application.
ABSTRACT
A rating voltage of 150 and 200 V split-gate trench (SGT) power metal-oxide- semiconductor field-effect transistor (Power MOSFET) with different epitaxial layers was proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 and 200 V SGT power MOSFET, we used a multiple epitaxies (EPIs) structure to design it and compared other single-EPI and double-EPIs devices based on the same fabrication process. We found that the bottom epitaxial (EPI) layer of a double-EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce the Ron,sp. Therefore, the double-EPIs device has more flexibility to achieve a lower Ron,sp than the single-EPI one. When the required voltage is over 100 V, the on-state resistance (Ron) of double-EPIs device is no longer satisfying our expectations. A triple-EPIs structure was designed and studied, to reduce its Ron, without sacrificing the breakdown voltage. We used an Integrated System Engineering-Technology Computer-Aided Design (ISE-TCAD) simulator to investigate and study the 150 V SGT power MOSFETs with different EPI structures, by modulating the thickness and resistivity of each EPI layer. The simulated Ron,sp of a 150 V triple-EPIs device is only 62% and 18.3% of that for the double-EPIs and single-EPI structure, respectively.
