Author Correction: Memristive synapses connect brain and silicon spiking neurons.

An amendment to this paper has been published and can be accessed via a link at the top of the paper.

Memristive synapses connect brain and silicon spiking neurons.

Brain function relies on circuits of spiking neurons with synapses playing the key role of merging transmission with memory storage and processing. Electronics has made important advances to emulate neurons and synapses and brain-computer interfacing concepts that interlink brain and brain-inspired devices are beginning to materialise. We report on memristive links between brain and silicon spiking neurons that emulate transmission and plasticity properties of real synapses. A memristor paired with a metal-thin film titanium oxide microelectrode connects a silicon neuron to a neuron of the rat hippocampus. Memristive plasticity accounts for modulation of connection strength, while transmission is mediated by weighted stimuli through the thin film oxide leading to responses that resemble excitatory postsynaptic potentials. The reverse brain-to-silicon link is established through a microelectrode-memristor pair. On these bases, we demonstrate a three-neuron brain-silicon network where memristive synapses undergo long-term potentiation or depression driven by neuronal firing rates.

An Electrical Characterisation Methodology for Benchmarking Memristive Device Technologies.

The emergence of memristor technologies brings new prospects for modern electronics via enabling novel in-memory computing solutions and energy-efficient and scalable reconfigurable hardware implementations. Several competing memristor technologies have been presented with each bearing distinct performance metrics across multi-bit memory capacity, low-power operation, endurance, retention and stability. Application needs however are constantly driving the push towards higher performance, which necessitates the introduction of a standard benchmarking procedure for fair evaluation across distinct key metrics. Here we present an electrical characterisation methodology that amalgamates several testing protocols in an appropriate sequence adapted for memristors benchmarking needs, in a technology-agnostic manner. Our approach is designed to extract information on all aspects of device behaviour, ranging from deciphering underlying physical mechanisms to assessing different aspects of electrical performance and even generating data-driven device-specific models. Importantly, it relies solely on standard electrical characterisation instrumentation that is accessible in most electronics laboratories and can thus serve as an independent tool for understanding and designing new memristive device technologies.

Impact of Line Edge Roughness on ReRAM Uniformity and Scaling.

We investigate the effects of Line Edge Roughness (LER) of electrode lines on the uniformity of Resistive Random Access Memory (ReRAM) device areas in cross-point architectures. To this end, a modeling approach is implemented based on the generation of 2D cross-point patterns with predefined and controlled LER and pattern parameters. The aim is to evaluate the significance of LER in the variability of device areas and their performances and to pinpoint the most critical parameters and conditions. It is found that conventional LER parameters may induce >10% area variability depending on pattern dimensions and cross edge/line correlations. Increased edge correlations in lines such as those that appeared in Double Patterning and Directed Self-assembly Lithography techniques lead to reduced area variability. Finally, a theoretical formula is derived to explain the numerical dependencies of the modeling method.

Spike sorting using non-volatile metal-oxide memristors.

Electrophysiological techniques have improved substantially over the past years to the point that neuroprosthetics applications are becoming viable. This evolution has been fuelled by the advancement of implantable microelectrode technologies that have followed their own version of Moore's scaling law. Similarly to electronics, however, excessive data-rates and strained power budgets require the development of more efficient computation paradigms for handling neural data in situ; in particular the computationally heavy task of events classification. Here, we demonstrate how the intrinsic analogue programmability of memristive devices can be exploited to perform spike-sorting on single devices. Leveraging the physical properties of nanoscale memristors allows us to demonstrate that these devices can capture enough information in neural signal for performing spike detection (shown previously) and spike sorting at no additional power cost.

Challenges hindering memristive neuromorphic hardware from going mainstream.

Memristive devices have elicited intense research in the past decade thanks to their inherent low voltage operation, multi-bit storage and cost-effective manufacturability. Nonetheless, several outstanding performance and manufacturability challenges have prevented the widespread industry adoption of redox-based memristive matrices. Here, we discuss these challenges in terms of key metrics and propose a roadmap towards realizing competitive memristive-based neuromorphic processing systems.

Seamlessly fused digital-analogue reconfigurable computing using memristors.

As the world enters the age of ubiquitous computing, the need for reconfigurable hardware operating close to the fundamental limits of energy consumption becomes increasingly pressing. Simultaneously, scaling-driven performance improvements within the framework of traditional analogue and digital design become progressively more restricted by fundamental physical constraints. Emerging nanoelectronics technologies bring forth new prospects yet a significant rethink of electronics design is required for realising their full potential. Here we lay the foundations of a design approach that fuses analogue and digital thinking by combining digital electronics with analogue memristive devices for achieving charge-based computation; information processing where every dissipated charge counts. This is realised by introducing memristive devices into standard logic gates, thus rendering them reconfigurable and capable of performing analogue computation at a power cost close to digital. The versatility and benefits of our approach are experimentally showcased through a hardware data clusterer and an analogue NAND gate.

Sub 100 nW Volatile Nano-Metal-Oxide Memristor as Synaptic-Like Encoder of Neuronal Spikes.

Advanced neural interfaces mediate a bioelectronic link between the nervous system and microelectronic devices, bearing great potential as innovative therapy for various diseases. Spikes from a large number of neurons are recorded leading to creation of big data that require online processing under most stringent conditions, such as minimal power dissipation and on-chip space occupancy. Here, we present a new concept where the inherent volatile properties of a nano-scale memristive device are used to detect and compress information on neural spikes as recorded by a multielectrode array. Simultaneously, and similarly to a biological synapse, information on spike amplitude and frequency is transduced in metastable resistive state transitions of the device, which is inherently capable of self-resetting and of continuous encoding of spiking activity. Furthermore, operating the memristor in a very high resistive state range reduces its average in-operando power dissipation to less than 100 nW, demonstrating the potential to build highly scalable, yet energy-efficient on-node processors for advanced neural interfaces.

Multibit memory operation of metal-oxide bi-layer memristors.

Emerging nanoionic memristive devices are considered as the memory technology of the future and have been winning a great deal of attention due to their ability to perform fast and at the expense of low-power and -space requirements. Their full potential is envisioned that can be fulfilled through their capacity to store multiple memory states per cell, which however has been constrained so far by issues affecting the long-term stability of independent states. Here, we introduce and evaluate a multitude of metal-oxide bi-layers and demonstrate the benefits from increased memory stability via multibit memory operation. We propose a programming methodology that allows for operating metal-oxide memristive devices as multibit memory elements with highly packed yet clearly discernible memory states. These states were found to correlate with the transport properties of the introduced barrier layers. We are demonstrating memory cells with up to 6.5 bits of information storage as well as excellent retention and power consumption performance. This paves the way for neuromorphic and non-volatile memory applications.

Improving Detection Accuracy of Memristor-Based Bio-Signal Sensing Platform.

Recently a novel neuronal activity sensor exploiting the intrinsic thresholded integrator capabilities of memristor devices has been proposed. Extracellular potentials captured by a standard bio-signal acquisition platform are fed into a memristive device which reacts to the input by changing its resistive state (RS) only when the signal ampitude exceeds a threshold. Thus, significant peaks in the neural signal can be stored as non-volatile changes in memristor resistive state whilst noise is effectively suppressed. However, as a memristor is subjected to increasing numbers of supra-threshold stimuli during practical operation, it accumulates (RS) changes and eventually saturates. This leads to severely redsignaluced neural activity detection capabilities. In this work we explore different signal processing and memristor operating procedure strategies in order to improve the detection rate of significant neuronal activity events. We analyse the data obtained from a single-memristive device biased with a reference neural recording and observe that performance can be improved markedly by a) increasing the frequency at which the memristor is reset to an initial resistive state where it is known to be highly responsive, b) appropriately preconditioning the input waveform through application of gain and offset in order to optimally exploit the intrinsic device behaviour. All results are validated by benchmarking obtained spike detection performance against a state-of-the-art template matching system utilising computationally-heavy, multi-dimensional, principal component analysis.

Resistive switching of Pt/TiO x /Pt devices fabricated on flexible Parylene-C substrates.

Pt/TiO x /Pt resistive switching (RS) devices are considered to be amongst the most promising candidates in memristor family and the technology transfer to flexible substrates could open the way to new opportunities for flexible memory implementations. Hence, an important goal is to achieve a fully flexible RS memory technology. Nonetheless, several fabrication challenges are present and must be solved prior to achieving reliable device fabrication and good electronic performances. Here, we propose a fabrication method for the successful transfer of Pt/TiO x /Pt stack onto flexible Parylene-C substrates. The devices were electrically characterised, exhibiting both digital and analogue memory characteristics, which are obtained by proper adjustment of pulsing schemes during tests. This approach could open new application possibilities of these devices in neuromorphic computing, data processing, implantable sensors and bio-compatible neural interfaces.

Real-time encoding and compression of neuronal spikes by metal-oxide memristors.

Advanced brain-chip interfaces with numerous recording sites bear great potential for investigation of neuroprosthetic applications. The bottleneck towards achieving an efficient bio-electronic link is the real-time processing of neuronal signals, which imposes excessive requirements on bandwidth, energy and computation capacity. Here we present a unique concept where the intrinsic properties of memristive devices are exploited to compress information on neural spikes in real-time. We demonstrate that the inherent voltage thresholds of metal-oxide memristors can be used for discriminating recorded spiking events from background activity and without resorting to computationally heavy off-line processing. We prove that information on spike amplitude and frequency can be transduced and stored in single devices as non-volatile resistive state transitions. Finally, we show that a memristive device array allows for efficient data compression of signals recorded by a multi-electrode array, demonstrating the technology's potential for building scalable, yet energy-efficient on-node processors for brain-chip interfaces.

Unsupervised learning in probabilistic neural networks with multi-state metal-oxide memristive synapses.

In an increasingly data-rich world the need for developing computing systems that cannot only process, but ideally also interpret big data is becoming continuously more pressing. Brain-inspired concepts have shown great promise towards addressing this need. Here we demonstrate unsupervised learning in a probabilistic neural network that utilizes metal-oxide memristive devices as multi-state synapses. Our approach can be exploited for processing unlabelled data and can adapt to time-varying clusters that underlie incoming data by supporting the capability of reversible unsupervised learning. The potential of this work is showcased through the demonstration of successful learning in the presence of corrupted input data and probabilistic neurons, thus paving the way towards robust big-data processors.

High Density Crossbar Arrays with Sub- 15 nm Single Cells via Liftoff Process Only.

Emerging nano-scale technologies are pushing the fabrication boundaries at their limits, for leveraging an even higher density of nano-devices towards reaching 4F(2)/cell footprint in 3D arrays. Here, we study the liftoff process limits to achieve extreme dense nanowires while ensuring preservation of thin film quality. The proposed method is optimized for attaining a multiple layer fabrication to reliably achieve 3D nano-device stacks of 32 × 32 nanowire arrays across 6-inch wafer, using electron beam lithography at 100 kV and polymethyl methacrylate (PMMA) resist at different thicknesses. The resist thickness and its geometric profile after development were identified to be the major limiting factors, and suggestions for addressing these issues are provided. Multiple layers were successfully achieved to fabricate arrays of 1 Ki cells that have sub- 15 nm nanowires distant by 28 nm across 6-inch wafer.

Investigation of the Switching Mechanism in TiO2-Based RRAM: A Two-Dimensional EDX Approach.

The next generation of nonvolatile memory storage may well be based on resistive switching in metal oxides. TiO2 as transition metal oxide has been widely used as active layer for the fabrication of a variety of multistate memory nanostructure devices. However, progress in their technological development has been inhibited by the lack of a thorough understanding of the underlying switching mechanisms. Here, we employed high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) combined with two-dimensional energy dispersive X-ray spectroscopy (2D EDX) to provide a novel, nanoscale view of the mechanisms involved. Our results suggest that the switching mechanism involves redistribution of both Ti and O ions within the active layer combined with an overall loss of oxygen that effectively render conductive filaments. Our study shows evidence of titanium movement in a 10 nm TiO2 thin-film through direct EDX mapping that provides a viable starting point for the improvement of the robustness and lifetime of TiO2-based resistive random access memory (RRAM).

Emulating short-term synaptic dynamics with memristive devices.

Neuromorphic architectures offer great promise for achieving computation capacities beyond conventional Von Neumann machines. The essential elements for achieving this vision are highly scalable synaptic mimics that do not undermine biological fidelity. Here we demonstrate that single solid-state TiO2 memristors can exhibit non-associative plasticity phenomena observed in biological synapses, supported by their metastable memory state transition properties. We show that, contrary to conventional uses of solid-state memory, the existence of rate-limiting volatility is a key feature for capturing short-term synaptic dynamics. We also show how the temporal dynamics of our prototypes can be exploited to implement spatio-temporal computation, demonstrating the memristors full potential for building biophysically realistic neural processing systems.

Implementation of a spike-based perceptron learning rule using TiO2-x memristors.

Synaptic plasticity plays a crucial role in allowing neural networks to learn and adapt to various input environments. Neuromorphic systems need to implement plastic synapses to obtain basic "cognitive" capabilities such as learning. One promising and scalable approach for implementing neuromorphic synapses is to use nano-scale memristors as synaptic elements. In this paper we propose a hybrid CMOS-memristor system comprising CMOS neurons interconnected through TiO2-x memristors, and spike-based learning circuits that modulate the conductance of the memristive synapse elements according to a spike-based Perceptron plasticity rule. We highlight a number of advantages for using this spike-based plasticity rule as compared to other forms of spike timing dependent plasticity (STDP) rules. We provide experimental proof-of-concept results with two silicon neurons connected through a memristive synapse that show how the CMOS plasticity circuits can induce stable changes in memristor conductances, giving rise to increased synaptic strength after a potentiation episode and to decreased strength after a depression episode.

Coexistence of memory resistance and memory capacitance in TiO2 solid-state devices.

This work exploits the coexistence of both resistance and capacitance memory effects in TiO2-based two-terminal cells. Our Pt/TiO2/TiO x /Pt devices exhibit an interesting combination of hysteresis and non-zero crossing in their current-voltage (I-V) characteristic that indicates the presence of capacitive states. Our experimental results demonstrate that both resistance and capacitance states can be simultaneously set via either voltage cycling and/or voltage pulses. We argue that these state modulations occur due to bias-induced reduction of the TiO x active layer via the displacement of ionic species.

Stochastic switching of TiO2-based memristive devices with identical initial memory states.

In this work, we show that identical TiO2-based memristive devices that possess the same initial resistive states are only phenomenologically similar as their internal structures may vary significantly, which could render quite dissimilar switching dynamics. We experimentally demonstrated that the resistive switching of practical devices with similar initial states could occur at different programming stimuli cycles. We argue that similar memory states can be transcribed via numerous distinct active core states through the dissimilar reduced TiO2-x filamentary distributions. Our hypothesis was finally verified via simulated results of the memory state evolution, by taking into account dissimilar initial filamentary distribution.

Memory impedance in TiO2 based metal-insulator-metal devices.

Large attention has recently been given to a novel technology named memristor, for having the potential of becoming the new electronic device standard. Yet, its manifestation as the fourth missing element is rather controversial among scientists. Here we demonstrate that TiO2-based metal-insulator-metal devices are more than just a memory-resistor. They possess resistive, capacitive and inductive components that can concurrently be programmed; essentially exhibiting a convolution of memristive, memcapacitive and meminductive effects. We show how non-zero crossing current-voltage hysteresis loops can appear and we experimentally demonstrate their frequency response as memcapacitive and meminductive effects become dominant.