Hybrid Precision Floating-Point (HPFP) Selection to Optimize Hardware-Constrained Accelerator for CNN Training.

The rapid advancement in AI requires efficient accelerators for training on edge devices, which often face challenges related to the high hardware costs of floating-point arithmetic operations. To tackle these problems, efficient floating-point formats inspired by block floating-point (BFP), such as Microsoft Floating Point (MSFP) and FlexBlock (FB), are emerging. However, they have limited dynamic range and precision for the smaller magnitude values within a block due to the shared exponent. This limits the BFP's ability to train deep neural networks (DNNs) with diverse datasets. This paper introduces the hybrid precision (HPFP) selection algorithms, designed to systematically reduce precision and implement hybrid precision strategies, thereby balancing layer-wise arithmetic operations and data path precision to address the shortcomings of traditional floating-point formats. Reducing the data bit width with HPFP allows more read/write operations from memory per cycle, thereby decreasing off-chip data access and the size of on-chip memories. Unlike traditional reduced precision formats that use BFP for calculating partial sums and accumulating those partial sums in 32-bit Floating Point (FP32), HPFP leads to significant hardware savings by performing all multiply and accumulate operations in reduced floating-point format. For evaluation, two training accelerators for the YOLOv2-Tiny model were developed, employing distinct mixed precision strategies, and their performance was benchmarked against an accelerator utilizing a conventional brain floating point of 16 bits (Bfloat16). The HPFP selection, employing 10 bits for the data path of all layers and for the arithmetic of layers requiring low precision, along with 12 bits for layers requiring higher precision, results in a 49.4% reduction in energy consumption and a 37.5% decrease in memory access. This is achieved with only a marginal mean Average Precision (mAP) degradation of 0.8% when compared to an accelerator based on Bfloat16. This comparison demonstrates that the proposed accelerator based on HPFP can be an efficient approach to designing compact and low-power accelerators without sacrificing accuracy.

Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing Chip.

In this paper, we propose a compact and low-power mixed-signal approach to implementing convolutional operators that are often responsible for most of the chip area and power consumption of Convolutional Neural Network (CNN) processing chips. The convolutional operators consist of several multiply-and-accumulate (MAC) units. MAC units are the primary components that process convolutional layers and fully connected layers of CNN models. Analog implementation of MAC units opens a new paradigm for realizing low-power CNN processing chips, benefiting from less power and area consumption. The proposed mixed-signal convolutional operator comprises low-power binary-weighted current steering digital-to-analog conversion (DAC) circuits and accumulation capacitors. Compared with a conventional binary-weighted DAC, the proposed circuit benefits from optimum accuracy, smaller area, and lower power consumption due to its symmetric design. The proposed convolutional operator takes as input a set of 9-bit digital input feature data and weight parameters of the convolutional filter. It then calculates the convolutional filter's result and accumulates the resulting voltage on capacitors. In addition, the convolutional operator employs a novel charge-sharing technique to process negative MAC results. We propose an analog max-pooling circuit that instantly selects the maximum input voltage. To demonstrate the performance of the proposed mixed-signal convolutional operator, we implemented a CNN processing chip consisting of 3 analog convolutional operators, with each operator processing a 3 × 3 kernel. This chip contains 27 MAC circuits, an analog max-pooling, and an analog-to-digital conversion (ADC) circuit. The mixed-signal CNN processing chip is implemented using a CMOS 55 nm process, which occupies a silicon area of 0.0559 mm2 and consumes an average power of 540.6 µW. The proposed mixed-signal CNN processing chip offers an area reduction of 84.21% and an energy reduction of 91.85% compared with a conventional digital CNN processing chip. Moreover, another CNN processing chip is implemented with more analog convolutional operators to demonstrate the operation and structure of an example convolutional layer of a CNN model. Therefore, the proposed analog convolutional operator can be adapted in various CNN models as an alternative to digital counterparts.

A Compact and Low-Power SoC Design for Spiking Neural Network Based on Current Multiplier Charge Injector Synapse.

This paper presents a compact analog system-on-chip (SoC) implementation of a spiking neural network (SNN) for low-power Internet of Things (IoT) applications. The low-power implementation of an SNN SoC requires the optimization of not only the SNN model but also the architecture and circuit designs. In this work, the SNN has been constituted from the analog neuron and synaptic circuits, which are designed to optimize both the chip area and power consumption. The proposed synapse circuit is based on a current multiplier charge injector (CMCI) circuit, which can significantly reduce power consumption and chip area compared with the previous work while allowing for design scalability for higher resolutions. The proposed neuron circuit employs an asynchronous structure, which makes it highly sensitive to input synaptic currents and enables it to achieve higher energy efficiency. To compare the performance of the proposed SoC in its area and power consumption, we implemented a digital SoC for the same SNN model in FPGA. The proposed SNN chip, when trained using the MNIST dataset, achieves a classification accuracy of 96.56%. The presented SNN chip has been implemented using a 65 nm CMOS process for fabrication. The entire chip occupies 0.96 mm2 and consumes an average power of 530 µW, which is 200 times lower than its digital counterpart.

Security Requirements and Challenges of 6G Technologies and Applications.

After implementing 5G technology, academia and industry started researching 6th generation wireless network technology (6G). 6G is expected to be implemented around the year 2030. It will offer a significant experience for everyone by enabling hyper-connectivity between people and everything. In addition, it is expected to extend mobile communication possibilities where earlier generations could not have developed. Several potential technologies are predicted to serve as the foundation of 6G networks. These include upcoming and current technologies such as post-quantum cryptography, artificial intelligence (AI), machine learning (ML), enhanced edge computing, molecular communication, THz, visible light communication (VLC), and distributed ledger (DL) technologies such as blockchain. From a security and privacy perspective, these developments need a reconsideration of prior security traditional methods. New novel authentication, encryption, access control, communication, and malicious activity detection must satisfy the higher significant requirements of future networks. In addition, new security approaches are necessary to ensure trustworthiness and privacy. This paper provides insights into the critical problems and difficulties related to the security, privacy, and trust issues of 6G networks. Moreover, the standard technologies and security challenges per each technology are clarified. This paper introduces the 6G security architecture and improvements over the 5G architecture. We also introduce the security issues and challenges of the 6G physical layer. In addition, the AI/ML layers and the proposed security solution in each layer are studied. The paper summarizes the security evolution in legacy mobile networks and concludes with their security problems and the most essential 6G application services and their security requirements. Finally, this paper provides a complete discussion of 6G networks' trustworthiness and solutions.

Optimal Architecture of Floating-Point Arithmetic for Neural Network Training Processors.

The convergence of artificial intelligence (AI) is one of the critical technologies in the recent fourth industrial revolution. The AIoT (Artificial Intelligence Internet of Things) is expected to be a solution that aids rapid and secure data processing. While the success of AIoT demanded low-power neural network processors, most of the recent research has been focused on accelerator designs only for inference. The growing interest in self-supervised and semi-supervised learning now calls for processors offloading the training process in addition to the inference process. Incorporating training with high accuracy goals requires the use of floating-point operators. The higher precision floating-point arithmetic architectures in neural networks tend to consume a large area and energy. Consequently, an energy-efficient/compact accelerator is required. The proposed architecture incorporates training in 32 bits, 24 bits, 16 bits, and mixed precisions to find the optimal floating-point format for low power and smaller-sized edge device. The proposed accelerator engines have been verified on FPGA for both inference and training of the MNIST image dataset. The combination of 24-bit custom FP format with 16-bit Brain FP has achieved an accuracy of more than 93%. ASIC implementation of this optimized mixed-precision accelerator using TSMC 65nm reveals an active area of 1.036 × 1.036 mm2 and energy consumption of 4.445 µJ per training of one image. Compared with 32-bit architecture, the size and the energy are reduced by 4.7 and 3.91 times, respectively. Therefore, the CNN structure using floating-point numbers with an optimized data path will significantly contribute to developing the AIoT field that requires a small area, low energy, and high accuracy.

Centralized Threshold Key Generation Protocol Based on Shamir Secret Sharing and HMAC Authentication.

Many group key management protocols have been proposed to manage key generation and distribution of vehicular communication. However, most of them suffer from high communication and computation costs due to the complex elliptic curve and bilinear pairing cryptography. Many shared secret protocols have been proposed using polynomial evaluation and interpolation to solve the previous complexity issues. This paper proposes an efficient centralized threshold shared secret protocol based on the Shamir secret sharing technique and supporting key authentication using Hashed Message Authentication Code Protocol (HMAC). The proposed protocol allows the group manager to generate a master secret key for a group of n vehicles and split this key into secret shares; each share is distributed securely to every group member. t-of-n vehicles must recombine their secret shares and recover the original secret key. The acceptance of the recovered key is based on the correctness of the received HMAC signature to verify the group manager's identity and ensure the key confidentiality. The proposed protocol is unconditionally secure and unbreakable using infinite computing power as t, or more than t secret shares are required to reconstruct the key. In contrast, attackers with t-1 secret shares cannot leak any information about the original secret key. Moreover, the proposed protocol reduces the computation cost due to using polynomial evaluation to generate the secret key and interpolation to recover the secret key, which is very simple and lightweight compared with the discrete logarithm computation cost in previous protocols. In addition, utilizing a trusted group manager that broadcasts some public information is important for the registered vehicles to reconstruct the key and eliminate secure channels between vehicles. The proposed protocol reduces the communication cost in terms of transmitted messages between vehicles from 2(t-1) messages in previous shared secret protocols to zero messages. Moreover, it reduces the received messages at vehicles from 2t to two messages. At the same time, it allows vehicles to store only a single secret share compared with other shared secret protocols that require storage of t secret shares. The proposed protocol security level outperforms the other shared secret protocols security, as it supports key authentication and confidentiality using HMAC that prevents attackers from compromising or faking the key.

A Key Management Protocol Based on the Hash Chain Key Generation for Securing LoRaWAN Networks.

Recently, many Low Power Wide Area Network (LPWAN) protocols have been proposed for securing resource-constrained Internet of Things (IoT) devices with negligible power consumption. The Long Range Wide Area Network (LoRaWAN) is a low power communication protocol that supports message authentication, integrity, and encryption using two-session preshared secret keys. However, although the LoRaWAN supports some security functions, it suffers from session key generation and key update problems. This motivates us to introduce a new key management protocol that resolves the LoRaWAN problems and supports key updates. The proposed protocol is based on hash chain generation using a one-way hash function. Network entities share a common hash chain of n key elements to allow using a unique signing key per message. We also propose a salt hashing algorithm that encrypts the original keys into a different form to avoid the physical attacks at the end device side. We analyzed the proposed key generation performance in terms of the computation time, the required storage, and the communication overhead. We implemented and tested the proposed key generation protocol using the NS-3 network simulator. The proposed lightweight key generation protocol significantly enhances the security of the original LoRaWAN at a negligible overhead. The proposed protocol reduces the power consumption and transmission time by two times compared with some previous protocols. In addition, the proposed key generation protocol can resist attacks, such as key compromising attacks and replay attacks, and it supports the Perfect Forward Secrecy, which was not supported by LoRaWAN.

A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits.

To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm2 chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW-20 times lower than the digital implementation.

Multi-Zone Authentication and Privacy-Preserving Protocol (MAPP) Based On the Bilinear Pairing Cryptography for 5G-V2X.

5G-Vehicle-to-Everything (5G-V2X) supports high-reliability and low latency autonomous services and applications. Proposing an efficient security solution that supports multi-zone broadcast authentication and satisfies the 5G requirement is a critical challenge. In The 3rd Generation Partnership Project (3GPP) Release 16 standard, for Cellular- Vehicle-to-Everything (C-V2X) single-cell communication is suggested to reuse the IEEE1609.2 security standard that utilizes the Public Key Infrastructure (PKI) cryptography. PKI-based solutions provide a high-security level, however, it suffers from high communication and computation overhead, due to the large size of the attached certificate and signature. In this study, we propose a light-weight Multi-Zone Authentication and Privacy-Preserving Protocol (MAPP) based on the bilinear pairing cryptography and short-size signature. MAPP protocol provides three different authentication methods that enable a secure broadcast authentication over multiple zones of large-scale base stations, using a single message and a single short signature. We also propose a centralized dynamic key generation method for multiple zones. We implemented and analyzed the proposed key generation and authentication methods using an authentication simulator and a bilinear pairing library. The proposed methods significantly reduce the signature generation time by 16 times-80 times, as compared to the previous methods. Additionally, the proposed methods significantly reduced the signature verification time by 10 times-16 times, as compared to the two previous methods. The three proposed authentication methods achieved substantial speed-up in the signature generation time and verification time, using a short bilinear pairing signature.

An Ultra-Wide Load Range Voltage Converter Using Proactive Phase Frequency Modulation for IoT Sensors.

Modern sensor nodes have multiple operating states, which causes a conventional voltage converter to perform poorly over a wide load range of the operating states. This paper proposes a voltage converter whose switching frequency and output voltage are proactively adjusted to maintain high conversion efficiency. This allows the converter to exploit a wider frequency range to cover a wide load range. In addition, the proposed converter uses multiple smaller capacitor banks and employs multiphase operation to provide low output ripple voltage. A distributed topology for non-overlapping signal generation is proposed and used in the converter to minimize the number of wires running from connecting the controller to the converter. The proposed voltage converter has been implemented in a chip using a 0.13 um CMOS process. The measurement results demonstrate the ability to support a wide load range of 10 µA to 10 mA, for switching frequencies ranging from 100 kHz to 200 MHz, while providing an efficiency of above 80%.

A Scalable and Secure Group Key Management Method for Secure V2V Communication.

Safety applications based on vehicle-to-everything (V2X) communications can significantly enhance road safety and reduce traffic fatalities. Ensuring the security and privacy of the vehicular network is essential for the widespread adoption of V2X communications for commercial use. V2X safety and service applications require periodic broadcast communications among all the vehicles. However, compared to unicast communication, it is extremely challenging to provide broadcast communication with network security requirements such as confidentiality, in infotainment contents distribution, sensor data sharing, and security credentials management services. To address the providing confidentiality of vehicle-to-vehicle (V2V) broadcasting, we propose a group key management and message encryption method that is secure, lightweight, and scalable. The proposed group key management method can efficiently handle various scenarios like a node joining or leaving the group, with scalable rekeying algorithms. It employs a distributed and scalable architecture that offers several advantages such as the reduction of the key management overhead and the enhancement of the security level by keeping the key sizes with large networks. In addition, the proposed method employs a lightweight matrix-based encryption algorithm that can be easily applicable with the proposed group key management method. Further, we have implemented the proposed method and evaluated the performance using a V2V network simulator with several networks of highly dynamic group members. The simulation results show that the proposed method can reduce computation time for group key generation and message encryption by more than 80% compared to existing methods.

Comparative Experiments of V2X Security Protocol Based on Hash Chain Cryptography.

Vehicle-to-everything (V2X) is the communication technology designed to support road safety for drivers and autonomous driving. The light-weight security solution is crucial to meet the real-time needs of on-board V2X applications. However, most of the recently proposed V2X security protocols-based on the Elliptic Curve Digital Signature Algorithm (ECDSA)-are not efficient enough to support fast processing and reduce the communication overhead between vehicles. ECDSA provides a high-security level at the cost of excessive communication and computation overhead, which motivates us to propose a light-weight message authentication and privacy preservation protocol for V2X communications. The proposed protocol achieves highly secure message authentication at a substantially lower cost by introducing a hash chain of secret keys for a Message Authentication Code (MAC). We implemented the proposed protocol using commercial V2X devices to prove its performance advantages over the standard and non-standard protocols. We constructed real V2X networks using commercial V2X devices that run our implemented protocol. Our extensive experiments with real networks demonstrate that the proposed protocol reduces the communication overhead by 6 times and computation overhead by more than 100 times compared with the IEEE1609.2 standard. Moreover, the proposed protocol reduces the communication overhead by 4 times and the computation overhead by up to 100 times compared with a non-standard security protocol, TESLA. The proposed protocol substantially reduces the average end-to-end delay to 2.5 ms, which is a 24- and 28-fold reduction, respectively, compared with the IEEE1609 and TESLA protocols.

CMOS Capacitive Fingerprint Sensor Based on Differential Sensing Circuit with Noise Cancellation.

In this paper, we introduce a differential sensing technique for CMOS capacitive fingerprint detection. It employs a new capacitive-sensing cell structure with charge sharing detection and readout circuit. The proposed technique also can eliminate the effect of parasitic capacitances by employing parasitic insensitive switched-capacitor structure and so increases the sensitivity even under severe noisy conditions. It can also overcome the performance degradation caused by various conditions of finger surface by using a differential integrator and adjusting its number of integrations. In addition, the proposed architecture allows parallel detection of all sensing channels. It can, therefore, substantially speed up the detection process compared with conventional architectures. We implemented a prototype fingerprint sensor chip with an array of 20 × 16 sensor cells using a 130 nm CMOS process. Simulation experiments demonstrated that the proposed architecture provided an SNR gain of 54 dB, whereas a conventional single line sensing gives an SNR gain of only 13 dB.

Slowest local operators in quantum spin chains.

We numerically construct slowly relaxing local operators in a nonintegrable spin-1/2 chain. Restricting the support of the operator to M consecutive spins along the chain, we exhaustively search for the operator that minimizes the Frobenius norm of the commutator with the Hamiltonian. We first show that the Frobenius norm bounds the time scale of relaxation of the operator at high temperatures. We find operators with significantly slower relaxation than the slowest simple "hydrodynamic" mode due to energy diffusion. Then we examine some properties of the nontrivial slow operators. Using both exhaustive search and tensor network techniques, we find similar slowly relaxing operators for a Floquet spin chain; this system is hydrodynamically "trivial," with no conservation laws restricting their dynamics. We argue that such slow relaxation may be a generic feature following from locality and unitarity.

Thermalization of entanglement.

We explore the dynamics of the entanglement entropy near equilibrium in highly entangled pure states of two quantum-chaotic spin chains undergoing unitary time evolution. We examine the relaxation to equilibrium from initial states with either less or more entanglement entropy than the equilibrium value, as well as the dynamics of the spontaneous fluctuations of the entanglement that occur in equilibrium. For the spin chain with a time-independent Hamiltonian and thus an extensive conserved energy, we find slow relaxation of the entanglement entropy near equilibration. Such slow relaxation is absent in a Floquet spin chain with a Hamiltonian that is periodic in time and thus has no local conservation law. Therefore, we argue that slow diffusive energy transport is responsible for the slow relaxation of the entanglement entropy in the Hamiltonian system.

Modeling of memristive and memcapacitive behaviors in metal-oxide junctions.

Memristive behavior has been clearly addressed through growth and shrinkage of thin filaments in metal-oxide junctions. Capacitance change has also been observed, raising the possibility of using them as memcapacitors. Therefore, this paper proves that metal-oxide junctions can behave as a memcapacitor element by analyzing its characteristics and modeling its memristive and memcapacitive behaviors. We develop two behavioral modeling techniques: charge-dependent memcapacitor model and voltage-dependent memcapacitor model. A new physical model for metal-oxide junctions is presented based on conducting filaments variations, and its effect on device capacitance and resistance. In this model, we apply the exponential nature of growth and shrinkage of thin filaments and use Simmons' tunneling equation to calculate the tunneling current. Simulation results show how the variations of practical device parameters can change the device behavior. They clarify the basic conditions for building a memcapacitor device with negligible change in resistance.

Testing whether all eigenstates obey the eigenstate thermalization hypothesis.

We ask whether the eigenstate thermalization hypothesis (ETH) is valid in a strong sense: in the limit of an infinite system, every eigenstate is thermal. We examine expectation values of few-body operators in highly excited many-body eigenstates and search for "outliers," the eigenstates that deviate the most from ETH. We use exact diagonalization of two one-dimensional nonintegrable models: a quantum Ising chain with transverse and longitudinal fields, and hard-core bosons at half-filling with nearest- and next-nearest-neighbor hopping and interaction. We show that even the most extreme outliers appear to obey ETH as the system size increases and thus provide numerical evidences that support ETH in this strong sense. Finally, periodically driving the Ising Hamiltonian, we show that the eigenstates of the corresponding Floquet operator obey ETH even more closely. We attribute this better thermalization to removing the constraint of conservation of the total energy.

Eigenstate thermalization and representative states on subsystems.

We consider a quantum system A∪B made up of degrees of freedom that can be partitioned into spatially disjoint regions A and B. When the full system is in a pure state in which regions A and B are entangled, the quantum mechanics of region A described without reference to its complement is traditionally assumed to require a reduced density matrix on A. While this is certainly true as an exact matter, we argue that under many interesting circumstances expectation values of typical operators anywhere inside A can be computed from a suitable pure state on A alone, with a controlled error. We use insights from quantum statistical mechanics-specifically the eigenstate thermalization hypothesis (ETH)-to argue for the existence of such "representative states."

Ballistic spreading of entanglement in a diffusive nonintegrable system.

We study the time evolution of the entanglement entropy of a one-dimensional nonintegrable spin chain, starting from random nonentangled initial pure states. We use exact diagonalization of a nonintegrable quantum Ising chain with transverse and longitudinal fields to obtain the exact quantum dynamics. We show that the entanglement entropy increases linearly with time before finite-size saturation begins, demonstrating a ballistic spreading of the entanglement, while the energy transport in the same system is diffusive. Thus, we explicitly demonstrate that the spreading of entanglement is much faster than the energy diffusion in this nonintegrable system.